fold fp_round(fp_round(x)) -> fp_round(x).

[oota-llvm.git] / lib / CodeGen / SelectionDAG / ScheduleDAGRRList.cpp

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 6ea7c80687820ec878251f7c200c7edaaed91816..05ba46d6ac6cf9f32c80a6adc28aeca2574914d7 100644 (file)
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -18,7 +18,6 @@
 #define DEBUG_TYPE "pre-RA-sched"
 #include "llvm/CodeGen/ScheduleDAG.h"
 #include "llvm/CodeGen/SchedulerRegistry.h"
-#include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/Target/MRegisterInfo.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetMachine.h"
@@ -149,10 +148,11 @@ void ScheduleDAGRRList::CommuteNodesToReducePressure() {
     if (!SU || !SU->Node) continue;
     if (SU->isCommutable) {
       unsigned Opc = SU->Node->getTargetOpcode();
-      unsigned NumRes = TII->getNumDefs(Opc);
+      const TargetInstrDesc &TID = TII->get(Opc);
+      unsigned NumRes = TID.getNumDefs();
       unsigned NumOps = CountOperands(SU->Node);
       for (unsigned j = 0; j != NumOps; ++j) {
-        if (TII->getOperandConstraint(Opc, j+NumRes, TOI::TIED_TO) == -1)
+        if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) == -1)
           continue;
 
         SDNode *OpN = SU->Node->getOperand(j).Val;
@@ -414,7 +414,7 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
 
   if (TryUnfold) {
     SmallVector<SDNode*, 4> NewNodes;
-    if (!MRI->unfoldMemoryOperand(DAG, N, NewNodes))
+    if (!TII->unfoldMemoryOperand(DAG, N, NewNodes))
       return NULL;
 
     DOUT << "Unfolding SU # " << SU->NodeNum << "\n";
@@ -431,14 +431,14 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
 
     SUnit *NewSU = NewSUnit(N);
     SUnitMap[N].push_back(NewSU);
-    const TargetInstrDescriptor *TID = &TII->get(N->getTargetOpcode());
-    for (unsigned i = 0; i != TID->numOperands; ++i) {
-      if (TID->getOperandConstraint(i, TOI::TIED_TO) != -1) {
+    const TargetInstrDesc &TID = TII->get(N->getTargetOpcode());
+    for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
+      if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
         NewSU->isTwoAddress = true;
         break;
       }
     }
-    if (TID->Flags & M_COMMUTABLE)
+    if (TID.isCommutable())
       NewSU->isCommutable = true;
     // FIXME: Calculate height / depth and propagate the changes?
     NewSU->Depth = SU->Depth;
@@ -622,10 +622,10 @@ void ScheduleDAGRRList::InsertCCCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,
 /// FIXME: Move to SelectionDAG?
 static MVT::ValueType getPhysicalRegisterVT(SDNode *N, unsigned Reg,
                                             const TargetInstrInfo *TII) {
-  const TargetInstrDescriptor &TID = TII->get(N->getTargetOpcode());
+  const TargetInstrDesc &TID = TII->get(N->getTargetOpcode());
   assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!");
-  unsigned NumRes = TID.numDefs;
-  for (const unsigned *ImpDef = TID.ImplicitDefs; *ImpDef; ++ImpDef) {
+  unsigned NumRes = TID.getNumDefs();
+  for (const unsigned *ImpDef = TID.getImplicitDefs(); *ImpDef; ++ImpDef) {
     if (Reg == *ImpDef)
       break;
     ++NumRes;
@@ -665,7 +665,7 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU,
     SDNode *Node = (i == 0) ? SU->Node : SU->FlaggedNodes[i-1];
     if (!Node || !Node->isTargetOpcode())
       continue;
-    const TargetInstrDescriptor &TID = TII->get(Node->getTargetOpcode());
+    const TargetInstrDesc &TID = TII->get(Node->getTargetOpcode());
     if (!TID.ImplicitDefs)
       continue;
     for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) {
@@ -1208,13 +1208,13 @@ static unsigned calcMaxScratches(const SUnit *SU) {
   for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
        I != E; ++I) {
     if (I->isCtrl) continue;  // ignore chain preds
-    if (I->Dep->Node->getOpcode() != ISD::CopyFromReg)
+    if (!I->Dep->Node || I->Dep->Node->getOpcode() != ISD::CopyFromReg)
       Scratches++;
   }
   for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
        I != E; ++I) {
     if (I->isCtrl) continue;  // ignore chain succs
-    if (I->Dep->Node->getOpcode() != ISD::CopyToReg)
+    if (!I->Dep->Node || I->Dep->Node->getOpcode() != ISD::CopyToReg)
       Scratches += 10;
   }
   return Scratches;
@@ -1288,10 +1288,11 @@ template<class SF>
 bool BURegReductionPriorityQueue<SF>::canClobber(SUnit *SU, SUnit *Op) {
   if (SU->isTwoAddress) {
     unsigned Opc = SU->Node->getTargetOpcode();
-    unsigned NumRes = TII->getNumDefs(Opc);
+    const TargetInstrDesc &TID = TII->get(Opc);
+    unsigned NumRes = TID.getNumDefs();
     unsigned NumOps = ScheduleDAG::CountOperands(SU->Node);
     for (unsigned i = 0; i != NumOps; ++i) {
-      if (TII->getOperandConstraint(Opc, i+NumRes, TOI::TIED_TO) != -1) {
+      if (TID.getOperandConstraint(i+NumRes, TOI::TIED_TO) != -1) {
         SDNode *DU = SU->Node->getOperand(i).Val;
         if ((*SUnitMap).find(DU) != (*SUnitMap).end() &&
             Op == (*SUnitMap)[DU][SU->InstanceNo])
@@ -1322,11 +1323,12 @@ static bool canClobberPhysRegDefs(SUnit *SuccSU, SUnit *SU,
                                   const TargetInstrInfo *TII,
                                   const MRegisterInfo *MRI) {
   SDNode *N = SuccSU->Node;
-  unsigned NumDefs = TII->getNumDefs(N->getTargetOpcode());
-  const unsigned *ImpDefs = TII->getImplicitDefs(N->getTargetOpcode());
+  unsigned NumDefs = TII->get(N->getTargetOpcode()).getNumDefs();
+  const unsigned *ImpDefs = TII->get(N->getTargetOpcode()).getImplicitDefs();
   if (!ImpDefs)
     return false;
-  const unsigned *SUImpDefs = TII->getImplicitDefs(SU->Node->getTargetOpcode());
+  const unsigned *SUImpDefs =
+    TII->get(SU->Node->getTargetOpcode()).getImplicitDefs();
   if (!SUImpDefs)
     return false;
   for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
@@ -1362,10 +1364,11 @@ void BURegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
       continue;
 
     unsigned Opc = Node->getTargetOpcode();
-    unsigned NumRes = TII->getNumDefs(Opc);
+    const TargetInstrDesc &TID = TII->get(Opc);
+    unsigned NumRes = TID.getNumDefs();
     unsigned NumOps = ScheduleDAG::CountOperands(Node);
     for (unsigned j = 0; j != NumOps; ++j) {
-      if (TII->getOperandConstraint(Opc, j+NumRes, TOI::TIED_TO) != -1) {
+      if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) != -1) {
         SDNode *DU = SU->Node->getOperand(j).Val;
         if ((*SUnitMap).find(DU) == (*SUnitMap).end())
           continue;