More constification of things. More comments added. No functionality

[oota-llvm.git] / lib / CodeGen / SelectionDAG / ScheduleDAGRRList.cpp

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index fcc2b8af28dba224cc1f05b7bdcb6413f32e7281..2cda59758ce6e79e98a36bd79edc5703c63fbbf3 100644 (file)
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -18,7 +18,7 @@
 #define DEBUG_TYPE "pre-RA-sched"
 #include "llvm/CodeGen/ScheduleDAG.h"
 #include "llvm/CodeGen/SchedulerRegistry.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetInstrInfo.h"
@@ -58,7 +58,6 @@ private:
   bool isBottomUp;
   
   /// AvailableQueue - The priority queue to use for the available SUnits.
-  ///a
   SchedulingPriorityQueue *AvailableQueue;
 
   /// LiveRegs / LiveRegDefs - A set of physical registers and their definition
@@ -107,8 +106,8 @@ private:
 void ScheduleDAGRRList::Schedule() {
   DOUT << "********** List Scheduling **********\n";
 
-  LiveRegDefs.resize(MRI->getNumRegs(), NULL);  
-  LiveRegCycles.resize(MRI->getNumRegs(), 0);
+  LiveRegDefs.resize(TRI->getNumRegs(), NULL);  
+  LiveRegCycles.resize(TRI->getNumRegs(), 0);
 
   // Build scheduling units.
   BuildSchedUnits();
@@ -148,10 +147,11 @@ void ScheduleDAGRRList::CommuteNodesToReducePressure() {
     if (!SU || !SU->Node) continue;
     if (SU->isCommutable) {
       unsigned Opc = SU->Node->getTargetOpcode();
-      unsigned NumRes = TII->getNumDefs(Opc);
-      unsigned NumOps = CountOperands(SU->Node);
+      const TargetInstrDesc &TID = TII->get(Opc);
+      unsigned NumRes = TID.getNumDefs();
+      unsigned NumOps = TID.getNumOperands() - NumRes;
       for (unsigned j = 0; j != NumOps; ++j) {
-        if (TII->getOperandConstraint(Opc, j+NumRes, TOI::TIED_TO) == -1)
+        if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) == -1)
           continue;
 
         SDNode *OpN = SU->Node->getOperand(j).Val;
@@ -430,14 +430,14 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
 
     SUnit *NewSU = NewSUnit(N);
     SUnitMap[N].push_back(NewSU);
-    const TargetInstrDescriptor *TID = &TII->get(N->getTargetOpcode());
-    for (unsigned i = 0; i != TID->numOperands; ++i) {
-      if (TID->getOperandConstraint(i, TOI::TIED_TO) != -1) {
+    const TargetInstrDesc &TID = TII->get(N->getTargetOpcode());
+    for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
+      if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
         NewSU->isTwoAddress = true;
         break;
       }
     }
-    if (TID->Flags & M_COMMUTABLE)
+    if (TID.isCommutable())
       NewSU->isCommutable = true;
     // FIXME: Calculate height / depth and propagate the changes?
     NewSU->Depth = SU->Depth;
@@ -621,10 +621,10 @@ void ScheduleDAGRRList::InsertCCCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,
 /// FIXME: Move to SelectionDAG?
 static MVT::ValueType getPhysicalRegisterVT(SDNode *N, unsigned Reg,
                                             const TargetInstrInfo *TII) {
-  const TargetInstrDescriptor &TID = TII->get(N->getTargetOpcode());
+  const TargetInstrDesc &TID = TII->get(N->getTargetOpcode());
   assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!");
-  unsigned NumRes = TID.numDefs;
-  for (const unsigned *ImpDef = TID.ImplicitDefs; *ImpDef; ++ImpDef) {
+  unsigned NumRes = TID.getNumDefs();
+  for (const unsigned *ImpDef = TID.getImplicitDefs(); *ImpDef; ++ImpDef) {
     if (Reg == *ImpDef)
       break;
     ++NumRes;
@@ -651,7 +651,7 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU,
         if (RegAdded.insert(Reg))
           LRegs.push_back(Reg);
       }
-      for (const unsigned *Alias = MRI->getAliasSet(Reg);
+      for (const unsigned *Alias = TRI->getAliasSet(Reg);
            *Alias; ++Alias)
         if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != I->Dep) {
           if (RegAdded.insert(*Alias))
@@ -664,7 +664,7 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU,
     SDNode *Node = (i == 0) ? SU->Node : SU->FlaggedNodes[i-1];
     if (!Node || !Node->isTargetOpcode())
       continue;
-    const TargetInstrDescriptor &TID = TII->get(Node->getTargetOpcode());
+    const TargetInstrDesc &TID = TII->get(Node->getTargetOpcode());
     if (!TID.ImplicitDefs)
       continue;
     for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) {
@@ -672,7 +672,7 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU,
         if (RegAdded.insert(*Reg))
           LRegs.push_back(*Reg);
       }
-      for (const unsigned *Alias = MRI->getAliasSet(*Reg);
+      for (const unsigned *Alias = TRI->getAliasSet(*Reg);
            *Alias; ++Alias)
         if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != SU) {
           if (RegAdded.insert(*Alias))
@@ -768,8 +768,8 @@ void ScheduleDAGRRList::ListScheduleBottomUp() {
           // Issue expensive cross register class copies.
           MVT::ValueType VT = getPhysicalRegisterVT(LRDef->Node, Reg, TII);
           const TargetRegisterClass *RC =
-            MRI->getPhysicalRegisterRegClass(VT, Reg);
-          const TargetRegisterClass *DestRC = MRI->getCrossCopyRegClass(RC);
+            TRI->getPhysicalRegisterRegClass(VT, Reg);
+          const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
           if (!DestRC) {
             assert(false && "Don't know how to copy this physical register!");
             abort();
@@ -898,7 +898,7 @@ void ScheduleDAGRRList::ListScheduleTopDown() {
   // All leaves to Available queue.
   for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
     // It is available if it has no predecessors.
-    if (SUnits[i].Preds.size() == 0 && &SUnits[i] != Entry) {
+    if (SUnits[i].Preds.empty() && &SUnits[i] != Entry) {
       AvailableQueue->push(&SUnits[i]);
       SUnits[i].isAvailable = true;
     }
@@ -1063,11 +1063,11 @@ namespace {
     std::vector<unsigned> SethiUllmanNumbers;
 
     const TargetInstrInfo *TII;
-    const MRegisterInfo *MRI;
+    const TargetRegisterInfo *TRI;
   public:
     explicit BURegReductionPriorityQueue(const TargetInstrInfo *tii,
-                                         const MRegisterInfo *mri)
-      : TII(tii), MRI(mri) {}
+                                         const TargetRegisterInfo *tri)
+      : TII(tii), TRI(tri) {}
 
     void initNodes(DenseMap<SDNode*, std::vector<SUnit*> > &sumap,
                    std::vector<SUnit> &sunits) {
@@ -1207,13 +1207,13 @@ static unsigned calcMaxScratches(const SUnit *SU) {
   for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
        I != E; ++I) {
     if (I->isCtrl) continue;  // ignore chain preds
-    if (I->Dep->Node->getOpcode() != ISD::CopyFromReg)
+    if (!I->Dep->Node || I->Dep->Node->getOpcode() != ISD::CopyFromReg)
       Scratches++;
   }
   for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
        I != E; ++I) {
     if (I->isCtrl) continue;  // ignore chain succs
-    if (I->Dep->Node->getOpcode() != ISD::CopyToReg)
+    if (!I->Dep->Node || I->Dep->Node->getOpcode() != ISD::CopyToReg)
       Scratches += 10;
   }
   return Scratches;
@@ -1287,10 +1287,11 @@ template<class SF>
 bool BURegReductionPriorityQueue<SF>::canClobber(SUnit *SU, SUnit *Op) {
   if (SU->isTwoAddress) {
     unsigned Opc = SU->Node->getTargetOpcode();
-    unsigned NumRes = TII->getNumDefs(Opc);
-    unsigned NumOps = ScheduleDAG::CountOperands(SU->Node);
+    const TargetInstrDesc &TID = TII->get(Opc);
+    unsigned NumRes = TID.getNumDefs();
+    unsigned NumOps = TID.getNumOperands() - NumRes;
     for (unsigned i = 0; i != NumOps; ++i) {
-      if (TII->getOperandConstraint(Opc, i+NumRes, TOI::TIED_TO) != -1) {
+      if (TID.getOperandConstraint(i+NumRes, TOI::TIED_TO) != -1) {
         SDNode *DU = SU->Node->getOperand(i).Val;
         if ((*SUnitMap).find(DU) != (*SUnitMap).end() &&
             Op == (*SUnitMap)[DU][SU->InstanceNo])
@@ -1319,13 +1320,14 @@ static bool hasCopyToRegUse(SUnit *SU) {
 /// physical register def.
 static bool canClobberPhysRegDefs(SUnit *SuccSU, SUnit *SU,
                                   const TargetInstrInfo *TII,
-                                  const MRegisterInfo *MRI) {
+                                  const TargetRegisterInfo *TRI) {
   SDNode *N = SuccSU->Node;
-  unsigned NumDefs = TII->getNumDefs(N->getTargetOpcode());
-  const unsigned *ImpDefs = TII->getImplicitDefs(N->getTargetOpcode());
+  unsigned NumDefs = TII->get(N->getTargetOpcode()).getNumDefs();
+  const unsigned *ImpDefs = TII->get(N->getTargetOpcode()).getImplicitDefs();
   if (!ImpDefs)
     return false;
-  const unsigned *SUImpDefs = TII->getImplicitDefs(SU->Node->getTargetOpcode());
+  const unsigned *SUImpDefs =
+    TII->get(SU->Node->getTargetOpcode()).getImplicitDefs();
   if (!SUImpDefs)
     return false;
   for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
@@ -1335,7 +1337,7 @@ static bool canClobberPhysRegDefs(SUnit *SuccSU, SUnit *SU,
     unsigned Reg = ImpDefs[i - NumDefs];
     for (;*SUImpDefs; ++SUImpDefs) {
       unsigned SUReg = *SUImpDefs;
-      if (MRI->regsOverlap(Reg, SUReg))
+      if (TRI->regsOverlap(Reg, SUReg))
         return true;
     }
   }
@@ -1361,10 +1363,11 @@ void BURegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
       continue;
 
     unsigned Opc = Node->getTargetOpcode();
-    unsigned NumRes = TII->getNumDefs(Opc);
-    unsigned NumOps = ScheduleDAG::CountOperands(Node);
+    const TargetInstrDesc &TID = TII->get(Opc);
+    unsigned NumRes = TID.getNumDefs();
+    unsigned NumOps = TID.getNumOperands() - NumRes;
     for (unsigned j = 0; j != NumOps; ++j) {
-      if (TII->getOperandConstraint(Opc, j+NumRes, TOI::TIED_TO) != -1) {
+      if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) != -1) {
         SDNode *DU = SU->Node->getOperand(j).Val;
         if ((*SUnitMap).find(DU) == (*SUnitMap).end())
           continue;
@@ -1383,9 +1386,9 @@ void BURegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
           if (!SuccSU->Node || !SuccSU->Node->isTargetOpcode())
             continue;
           // Don't constrain nodes with physical register defs if the
-          // predecessor can cloober them.
+          // predecessor can clobber them.
           if (SuccSU->hasPhysRegDefs) {
-            if (canClobberPhysRegDefs(SuccSU, SU, TII, MRI))
+            if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI))
               continue;
           }
           // Don't constraint extract_subreg / insert_subreg these may be
@@ -1577,9 +1580,9 @@ llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
                                                     SelectionDAG *DAG,
                                                     MachineBasicBlock *BB) {
   const TargetInstrInfo *TII = DAG->getTarget().getInstrInfo();
-  const MRegisterInfo *MRI = DAG->getTarget().getRegisterInfo();
+  const TargetRegisterInfo *TRI = DAG->getTarget().getRegisterInfo();
   return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true,
-                      new BURegReductionPriorityQueue<bu_ls_rr_sort>(TII, MRI));
+                      new BURegReductionPriorityQueue<bu_ls_rr_sort>(TII, TRI));
 }
 
 llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS,