/// Check to see if any of the pending instructions are ready to issue. If
/// so, add them to the available queue.
void ScheduleDAGRRList::ReleasePending() {
- assert(!EnableSchedCycles && "requires --enable-sched-cycles" );
+ if (!EnableSchedCycles) {
+ assert(PendingQueue.empty() && "pending instrs not allowed in this mode");
+ return;
+ }
// If the available queue is empty, it is safe to reset MinAvailableCycle.
if (AvailableQueue->empty())
/// Record this SUnit in the HazardRecognizer.
/// Does not update CurCycle.
void ScheduleDAGRRList::EmitNode(SUnit *SU) {
+ if (!EnableSchedCycles || HazardRec->getMaxLookAhead() == 0)
+ return;
+
+ // Check for phys reg copy.
+ if (!SU->getNode())
+ return;
+
switch (SU->getNode()->getOpcode()) {
default:
assert(SU->getNode()->isMachineOpcode() &&
RestoreHazardCheckerBottomUp();
- if (EnableSchedCycles)
- ReleasePending();
+ ReleasePending();
++NumBacktracks;
}
/// CopyAndMoveSuccessors - Clone the specified node and move its scheduled
/// successors to the newly created node.
SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
- if (SU->getNode()->getGluedNode())
- return NULL;
-
SDNode *N = SU->getNode();
if (!N)
return NULL;
+ if (SU->getNode()->getGluedNode())
+ return NULL;
+
SUnit *NewSU;
bool TryUnfold = false;
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {