-//===----- ScheduleDAGList.cpp - Reg pressure reduction list scheduler ----===//
+//===----- ScheduleDAGRRList.cpp - Reg pressure reduction list scheduler --===//
//
// The LLVM Compiler Infrastructure
//
static RegisterScheduler
burrListDAGScheduler("list-burr",
- " Bottom-up register reduction list scheduling",
+ "Bottom-up register reduction list scheduling",
createBURRListDAGScheduler);
static RegisterScheduler
tdrListrDAGScheduler("list-tdrr",
- " Top-down register reduction list scheduling",
+ "Top-down register reduction list scheduling",
createTDRRListDAGScheduler);
namespace {
/// it is top-down.
bool isBottomUp;
+ /// Fast - True if we are performing fast scheduling.
+ ///
bool Fast;
/// AvailableQueue - The priority queue to use for the available SUnits.
SchedulingPriorityQueue *AvailableQueue;
- /// LiveRegs / LiveRegDefs - A set of physical registers and their definition
+ /// LiveRegDefs - A set of physical registers and their definition
/// that are "live". These nodes must be scheduled before any other nodes that
/// modifies the registers can be scheduled.
- SmallSet<unsigned, 4> LiveRegs;
+ unsigned NumLiveRegs;
std::vector<SUnit*> LiveRegDefs;
std::vector<unsigned> LiveRegCycles;
void Schedule();
/// IsReachable - Checks if SU is reachable from TargetSU.
- bool IsReachable(SUnit *SU, SUnit *TargetSU);
+ bool IsReachable(const SUnit *SU, const SUnit *TargetSU);
/// willCreateCycle - Returns true if adding an edge from SU to TargetSU will
/// create a cycle.
/// DFS - make a DFS traversal and mark all nodes affected by the
/// edge insertion. These nodes will later get new topological indexes
/// by means of the Shift method.
- void DFS(SUnit *SU, int UpperBound, bool& HasLoop);
+ void DFS(const SUnit *SU, int UpperBound, bool& HasLoop);
/// Shift - reassign topological indexes for the nodes in the DAG
/// to preserve the topological ordering.
void ScheduleDAGRRList::Schedule() {
DOUT << "********** List Scheduling **********\n";
+ NumLiveRegs = 0;
LiveRegDefs.resize(TRI->getNumRegs(), NULL);
LiveRegCycles.resize(TRI->getNumRegs(), 0);
if (!Fast)
CommuteNodesToReducePressure();
-
- DOUT << "*** Final schedule ***\n";
- DEBUG(dumpSchedule());
- DOUT << "\n";
-
- // Emit in scheduled order
- EmitSchedule();
}
/// CommuteNodesToReducePressure - If a node is two-address and commutable, and
SUnit *SU = Sequence[i];
if (!SU || !SU->Node) continue;
if (SU->isCommutable) {
- unsigned Opc = SU->Node->getTargetOpcode();
+ unsigned Opc = SU->Node->getMachineOpcode();
const TargetInstrDesc &TID = TII->get(Opc);
unsigned NumRes = TID.getNumDefs();
unsigned NumOps = TID.getNumOperands() - NumRes;
if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) == -1)
continue;
- SDNode *OpN = SU->Node->getOperand(j).Val;
+ SDNode *OpN = SU->Node->getOperand(j).getNode();
SUnit *OpSU = isPassiveNode(OpN) ? NULL : &SUnits[OpN->getNodeId()];
if (OpSU && OperandSeen.count(OpSU) == 1) {
// Ok, so SU is not the last use of OpSU, but SU is two-address so
bool DoCommute = true;
for (unsigned k = 0; k < NumOps; ++k) {
if (k != j) {
- OpN = SU->Node->getOperand(k).Val;
+ OpN = SU->Node->getOperand(k).getNode();
OpSU = isPassiveNode(OpN) ? NULL : &SUnits[OpN->getNodeId()];
if (OpSU && OperandSeen.count(OpSU) == 1) {
DoCommute = false;
// expensive to copy the register. Make sure nothing that can
// clobber the register is scheduled between the predecessor and
// this node.
- if (LiveRegs.insert(I->Reg)) {
+ if (!LiveRegDefs[I->Reg]) {
+ ++NumLiveRegs;
LiveRegDefs[I->Reg] = I->Dep;
LiveRegCycles[I->Reg] = CurCycle;
}
I != E; ++I) {
if (I->Cost < 0) {
if (LiveRegCycles[I->Reg] == I->Dep->Cycle) {
- LiveRegs.erase(I->Reg);
+ assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
assert(LiveRegDefs[I->Reg] == SU &&
"Physical register dependency violated?");
+ --NumLiveRegs;
LiveRegDefs[I->Reg] = NULL;
LiveRegCycles[I->Reg] = 0;
}
I != E; ++I) {
CapturePred(I->Dep, SU, I->isCtrl);
if (I->Cost < 0 && SU->Cycle == LiveRegCycles[I->Reg]) {
- LiveRegs.erase(I->Reg);
+ assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
assert(LiveRegDefs[I->Reg] == I->Dep &&
"Physical register dependency violated?");
+ --NumLiveRegs;
LiveRegDefs[I->Reg] = NULL;
LiveRegCycles[I->Reg] = 0;
}
for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
I != E; ++I) {
if (I->Cost < 0) {
- if (LiveRegs.insert(I->Reg)) {
- assert(!LiveRegDefs[I->Reg] &&
- "Physical register dependency violated?");
+ if (!LiveRegDefs[I->Reg]) {
LiveRegDefs[I->Reg] = SU;
+ ++NumLiveRegs;
}
if (I->Dep->Cycle < LiveRegCycles[I->Reg])
LiveRegCycles[I->Reg] = I->Dep->Cycle;
}
/// IsReachable - Checks if SU is reachable from TargetSU.
-bool ScheduleDAGRRList::IsReachable(SUnit *SU, SUnit *TargetSU) {
+bool ScheduleDAGRRList::IsReachable(const SUnit *SU, const SUnit *TargetSU) {
// If insertion of the edge SU->TargetSU would create a cycle
// then there is a path from TargetSU to SU.
int UpperBound, LowerBound;
/// immediately after X in Index2Node.
void ScheduleDAGRRList::InitDAGTopologicalSorting() {
unsigned DAGSize = SUnits.size();
- std::vector<unsigned> InDegree(DAGSize);
std::vector<SUnit*> WorkList;
WorkList.reserve(DAGSize);
- std::vector<SUnit*> TopOrder;
- TopOrder.reserve(DAGSize);
+
+ Index2Node.resize(DAGSize);
+ Node2Index.resize(DAGSize);
// Initialize the data structures.
for (unsigned i = 0, e = DAGSize; i != e; ++i) {
SUnit *SU = &SUnits[i];
int NodeNum = SU->NodeNum;
unsigned Degree = SU->Succs.size();
- InDegree[NodeNum] = Degree;
+ // Temporarily use the Node2Index array as scratch space for degree counts.
+ Node2Index[NodeNum] = Degree;
// Is it a node without dependencies?
if (Degree == 0) {
}
}
+ int Id = DAGSize;
while (!WorkList.empty()) {
SUnit *SU = WorkList.back();
WorkList.pop_back();
- TopOrder.push_back(SU);
+ Allocate(SU->NodeNum, --Id);
for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
I != E; ++I) {
SUnit *SU = I->Dep;
- if (!--InDegree[SU->NodeNum])
+ if (!--Node2Index[SU->NodeNum])
// If all dependencies of the node are processed already,
// then the node can be computed now.
WorkList.push_back(SU);
}
}
- // Second pass, assign the actual topological order as node ids.
- int Id = 0;
-
- Index2Node.clear();
- Node2Index.clear();
- Index2Node.resize(DAGSize);
- Node2Index.resize(DAGSize);
Visited.resize(DAGSize);
- for (std::vector<SUnit*>::reverse_iterator TI = TopOrder.rbegin(),
- TE = TopOrder.rend();TI != TE; ++TI) {
- Allocate((*TI)->NodeNum, Id);
- Id++;
- }
-
#ifndef NDEBUG
// Check correctness of the ordering
for (unsigned i = 0, e = DAGSize; i != e; ++i) {
/// DFS - Make a DFS traversal to mark all nodes reachable from SU and mark
/// all nodes affected by the edge insertion. These nodes will later get new
/// topological indexes by means of the Shift method.
-void ScheduleDAGRRList::DFS(SUnit *SU, int UpperBound, bool& HasLoop) {
- std::vector<SUnit*> WorkList;
+void ScheduleDAGRRList::DFS(const SUnit *SU, int UpperBound, bool& HasLoop) {
+ std::vector<const SUnit*> WorkList;
WorkList.reserve(SUnits.size());
WorkList.push_back(SU);
TryUnfold = true;
}
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
- const SDOperand &Op = N->getOperand(i);
- MVT VT = Op.Val->getValueType(Op.ResNo);
+ const SDValue &Op = N->getOperand(i);
+ MVT VT = Op.getNode()->getValueType(Op.getResNo());
if (VT == MVT::Flag)
return NULL;
}
unsigned NumVals = N->getNumValues();
unsigned OldNumVals = SU->Node->getNumValues();
for (unsigned i = 0; i != NumVals; ++i)
- DAG.ReplaceAllUsesOfValueWith(SDOperand(SU->Node, i), SDOperand(N, i));
- DAG.ReplaceAllUsesOfValueWith(SDOperand(SU->Node, OldNumVals-1),
- SDOperand(LoadNode, 1));
+ DAG.ReplaceAllUsesOfValueWith(SDValue(SU->Node, i), SDValue(N, i));
+ DAG.ReplaceAllUsesOfValueWith(SDValue(SU->Node, OldNumVals-1),
+ SDValue(LoadNode, 1));
SUnit *NewSU = CreateNewSUnit(N);
assert(N->getNodeId() == -1 && "Node already inserted!");
N->setNodeId(NewSU->NodeNum);
- const TargetInstrDesc &TID = TII->get(N->getTargetOpcode());
+ const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
NewSU->isTwoAddress = true;
/// FIXME: Move to SelectionDAG?
static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
const TargetInstrInfo *TII) {
- const TargetInstrDesc &TID = TII->get(N->getTargetOpcode());
+ const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!");
unsigned NumRes = TID.getNumDefs();
for (const unsigned *ImpDef = TID.getImplicitDefs(); *ImpDef; ++ImpDef) {
/// whatever is necessary (i.e. backtracking or cloning) to make it possible.
bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU,
SmallVector<unsigned, 4> &LRegs){
- if (LiveRegs.empty())
+ if (NumLiveRegs == 0)
return false;
SmallSet<unsigned, 4> RegAdded;
I != E; ++I) {
if (I->Cost < 0) {
unsigned Reg = I->Reg;
- if (LiveRegs.count(Reg) && LiveRegDefs[Reg] != I->Dep) {
+ if (LiveRegDefs[Reg] && LiveRegDefs[Reg] != I->Dep) {
if (RegAdded.insert(Reg))
LRegs.push_back(Reg);
}
for (const unsigned *Alias = TRI->getAliasSet(Reg);
*Alias; ++Alias)
- if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != I->Dep) {
+ if (LiveRegDefs[*Alias] && LiveRegDefs[*Alias] != I->Dep) {
if (RegAdded.insert(*Alias))
LRegs.push_back(*Alias);
}
for (unsigned i = 0, e = SU->FlaggedNodes.size()+1; i != e; ++i) {
SDNode *Node = (i == 0) ? SU->Node : SU->FlaggedNodes[i-1];
- if (!Node || !Node->isTargetOpcode())
+ if (!Node || !Node->isMachineOpcode())
continue;
- const TargetInstrDesc &TID = TII->get(Node->getTargetOpcode());
+ const TargetInstrDesc &TID = TII->get(Node->getMachineOpcode());
if (!TID.ImplicitDefs)
continue;
for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) {
- if (LiveRegs.count(*Reg) && LiveRegDefs[*Reg] != SU) {
+ if (LiveRegDefs[*Reg] && LiveRegDefs[*Reg] != SU) {
if (RegAdded.insert(*Reg))
LRegs.push_back(*Reg);
}
for (const unsigned *Alias = TRI->getAliasSet(*Reg);
*Alias; ++Alias)
- if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != SU) {
+ if (LiveRegDefs[*Alias] && LiveRegDefs[*Alias] != SU) {
if (RegAdded.insert(*Alias))
LRegs.push_back(*Alias);
}
unsigned CurCycle = 0;
// Add root to Available queue.
if (!SUnits.empty()) {
- SUnit *RootSU = &SUnits[DAG.getRoot().Val->getNodeId()];
+ SUnit *RootSU = &SUnits[DAG.getRoot().getNode()->getNodeId()];
assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!");
RootSU->isAvailable = true;
AvailableQueue->push(RootSU);
bool operator()(const SUnit* left, const SUnit* right) const;
};
+ struct bu_ls_rr_fast_sort : public std::binary_function<SUnit*, SUnit*, bool>{
+ RegReductionPriorityQueue<bu_ls_rr_fast_sort> *SPQ;
+ bu_ls_rr_fast_sort(RegReductionPriorityQueue<bu_ls_rr_fast_sort> *spq)
+ : SPQ(spq) {}
+ bu_ls_rr_fast_sort(const bu_ls_rr_fast_sort &RHS) : SPQ(RHS.SPQ) {}
+
+ bool operator()(const SUnit* left, const SUnit* right) const;
+ };
+
struct td_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
RegReductionPriorityQueue<td_ls_rr_sort> *SPQ;
td_ls_rr_sort(RegReductionPriorityQueue<td_ls_rr_sort> *spq) : SPQ(spq) {}
N->getOperand(N->getNumOperands()-1).getValueType() != MVT::Flag;
}
+/// CalcNodeBUSethiUllmanNumber - Compute Sethi Ullman number for bottom up
+/// scheduling. Smaller number is the higher priority.
+static unsigned
+CalcNodeBUSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) {
+ unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum];
+ if (SethiUllmanNumber != 0)
+ return SethiUllmanNumber;
+
+ unsigned Extra = 0;
+ for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
+ I != E; ++I) {
+ if (I->isCtrl) continue; // ignore chain preds
+ SUnit *PredSU = I->Dep;
+ unsigned PredSethiUllman = CalcNodeBUSethiUllmanNumber(PredSU, SUNumbers);
+ if (PredSethiUllman > SethiUllmanNumber) {
+ SethiUllmanNumber = PredSethiUllman;
+ Extra = 0;
+ } else if (PredSethiUllman == SethiUllmanNumber && !I->isCtrl)
+ ++Extra;
+ }
+
+ SethiUllmanNumber += Extra;
+
+ if (SethiUllmanNumber == 0)
+ SethiUllmanNumber = 1;
+
+ return SethiUllmanNumber;
+}
+
+/// CalcNodeTDSethiUllmanNumber - Compute Sethi Ullman number for top down
+/// scheduling. Smaller number is the higher priority.
+static unsigned
+CalcNodeTDSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) {
+ unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum];
+ if (SethiUllmanNumber != 0)
+ return SethiUllmanNumber;
+
+ unsigned Opc = SU->Node ? SU->Node->getOpcode() : 0;
+ if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
+ SethiUllmanNumber = 0xffff;
+ else if (SU->NumSuccsLeft == 0)
+ // If SU does not have a use, i.e. it doesn't produce a value that would
+ // be consumed (e.g. store), then it terminates a chain of computation.
+ // Give it a small SethiUllman number so it will be scheduled right before
+ // its predecessors that it doesn't lengthen their live ranges.
+ SethiUllmanNumber = 0;
+ else if (SU->NumPredsLeft == 0 &&
+ (Opc != ISD::CopyFromReg || isCopyFromLiveIn(SU)))
+ SethiUllmanNumber = 0xffff;
+ else {
+ int Extra = 0;
+ for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
+ I != E; ++I) {
+ if (I->isCtrl) continue; // ignore chain preds
+ SUnit *PredSU = I->Dep;
+ unsigned PredSethiUllman = CalcNodeTDSethiUllmanNumber(PredSU, SUNumbers);
+ if (PredSethiUllman > SethiUllmanNumber) {
+ SethiUllmanNumber = PredSethiUllman;
+ Extra = 0;
+ } else if (PredSethiUllman == SethiUllmanNumber && !I->isCtrl)
+ ++Extra;
+ }
+
+ SethiUllmanNumber += Extra;
+ }
+
+ return SethiUllmanNumber;
+}
+
+
namespace {
template<class SF>
class VISIBILITY_HIDDEN RegReductionPriorityQueue
class VISIBILITY_HIDDEN BURegReductionPriorityQueue
: public RegReductionPriorityQueue<bu_ls_rr_sort> {
// SUnits - The SUnits for the current graph.
- const std::vector<SUnit> *SUnits;
+ std::vector<SUnit> *SUnits;
// SethiUllmanNumbers - The SethiUllman number for each node.
std::vector<unsigned> SethiUllmanNumbers;
const TargetRegisterInfo *TRI;
ScheduleDAGRRList *scheduleDAG;
- bool Fast;
public:
explicit BURegReductionPriorityQueue(const TargetInstrInfo *tii,
- const TargetRegisterInfo *tri,
- bool f)
- : TII(tii), TRI(tri), scheduleDAG(NULL), Fast(f) {}
+ const TargetRegisterInfo *tri)
+ : TII(tii), TRI(tri), scheduleDAG(NULL) {}
void initNodes(std::vector<SUnit> &sunits) {
SUnits = &sunits;
// Add pseudo dependency edges for two-address nodes.
- if (!Fast)
- AddPseudoTwoAddrDeps();
+ AddPseudoTwoAddrDeps();
// Calculate node priorities.
CalculateSethiUllmanNumbers();
}
void addNode(const SUnit *SU) {
- SethiUllmanNumbers.resize(SUnits->size(), 0);
- CalcNodeSethiUllmanNumber(SU);
+ unsigned SUSize = SethiUllmanNumbers.size();
+ if (SUnits->size() > SUSize)
+ SethiUllmanNumbers.resize(SUSize*2, 0);
+ CalcNodeBUSethiUllmanNumber(SU, SethiUllmanNumbers);
}
void updateNode(const SUnit *SU) {
SethiUllmanNumbers[SU->NodeNum] = 0;
- CalcNodeSethiUllmanNumber(SU);
+ CalcNodeBUSethiUllmanNumber(SU, SethiUllmanNumbers);
}
void releaseState() {
bool canClobber(const SUnit *SU, const SUnit *Op);
void AddPseudoTwoAddrDeps();
void CalculateSethiUllmanNumbers();
- unsigned CalcNodeSethiUllmanNumber(const SUnit *SU);
+ };
+
+
+ class VISIBILITY_HIDDEN BURegReductionFastPriorityQueue
+ : public RegReductionPriorityQueue<bu_ls_rr_fast_sort> {
+ // SUnits - The SUnits for the current graph.
+ const std::vector<SUnit> *SUnits;
+
+ // SethiUllmanNumbers - The SethiUllman number for each node.
+ std::vector<unsigned> SethiUllmanNumbers;
+ public:
+ explicit BURegReductionFastPriorityQueue() {}
+
+ void initNodes(std::vector<SUnit> &sunits) {
+ SUnits = &sunits;
+ // Calculate node priorities.
+ CalculateSethiUllmanNumbers();
+ }
+
+ void addNode(const SUnit *SU) {
+ unsigned SUSize = SethiUllmanNumbers.size();
+ if (SUnits->size() > SUSize)
+ SethiUllmanNumbers.resize(SUSize*2, 0);
+ CalcNodeBUSethiUllmanNumber(SU, SethiUllmanNumbers);
+ }
+
+ void updateNode(const SUnit *SU) {
+ SethiUllmanNumbers[SU->NodeNum] = 0;
+ CalcNodeBUSethiUllmanNumber(SU, SethiUllmanNumbers);
+ }
+
+ void releaseState() {
+ SUnits = 0;
+ SethiUllmanNumbers.clear();
+ }
+
+ unsigned getNodePriority(const SUnit *SU) const {
+ return SethiUllmanNumbers[SU->NodeNum];
+ }
+
+ private:
+ void CalculateSethiUllmanNumbers();
};
}
void addNode(const SUnit *SU) {
- SethiUllmanNumbers.resize(SUnits->size(), 0);
- CalcNodeSethiUllmanNumber(SU);
+ unsigned SUSize = SethiUllmanNumbers.size();
+ if (SUnits->size() > SUSize)
+ SethiUllmanNumbers.resize(SUSize*2, 0);
+ CalcNodeTDSethiUllmanNumber(SU, SethiUllmanNumbers);
}
void updateNode(const SUnit *SU) {
SethiUllmanNumbers[SU->NodeNum] = 0;
- CalcNodeSethiUllmanNumber(SU);
+ CalcNodeTDSethiUllmanNumber(SU, SethiUllmanNumbers);
}
void releaseState() {
private:
void CalculateSethiUllmanNumbers();
- unsigned CalcNodeSethiUllmanNumber(const SUnit *SU);
};
}
// Bottom up
bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
-
unsigned LPriority = SPQ->getNodePriority(left);
unsigned RPriority = SPQ->getNodePriority(right);
if (LPriority != RPriority)
return (left->NodeQueueId > right->NodeQueueId);
}
+bool
+bu_ls_rr_fast_sort::operator()(const SUnit *left, const SUnit *right) const {
+ unsigned LPriority = SPQ->getNodePriority(left);
+ unsigned RPriority = SPQ->getNodePriority(right);
+ if (LPriority != RPriority)
+ return LPriority > RPriority;
+ assert(left->NodeQueueId && right->NodeQueueId &&
+ "NodeQueueId cannot be zero");
+ return (left->NodeQueueId > right->NodeQueueId);
+}
+
bool
BURegReductionPriorityQueue::canClobber(const SUnit *SU, const SUnit *Op) {
if (SU->isTwoAddress) {
- unsigned Opc = SU->Node->getTargetOpcode();
+ unsigned Opc = SU->Node->getMachineOpcode();
const TargetInstrDesc &TID = TII->get(Opc);
unsigned NumRes = TID.getNumDefs();
unsigned NumOps = TID.getNumOperands() - NumRes;
for (unsigned i = 0; i != NumOps; ++i) {
if (TID.getOperandConstraint(i+NumRes, TOI::TIED_TO) != -1) {
- SDNode *DU = SU->Node->getOperand(i).Val;
+ SDNode *DU = SU->Node->getOperand(i).getNode();
if (DU->getNodeId() != -1 &&
Op->OrigNode == &(*SUnits)[DU->getNodeId()])
return true;
/// hasCopyToRegUse - Return true if SU has a value successor that is a
/// CopyToReg node.
-static bool hasCopyToRegUse(SUnit *SU) {
+static bool hasCopyToRegUse(const SUnit *SU) {
for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
I != E; ++I) {
if (I->isCtrl) continue;
- SUnit *SuccSU = I->Dep;
+ const SUnit *SuccSU = I->Dep;
if (SuccSU->Node && SuccSU->Node->getOpcode() == ISD::CopyToReg)
return true;
}
/// canClobberPhysRegDefs - True if SU would clobber one of SuccSU's
/// physical register defs.
-static bool canClobberPhysRegDefs(SUnit *SuccSU, SUnit *SU,
+static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU,
const TargetInstrInfo *TII,
const TargetRegisterInfo *TRI) {
SDNode *N = SuccSU->Node;
- unsigned NumDefs = TII->get(N->getTargetOpcode()).getNumDefs();
- const unsigned *ImpDefs = TII->get(N->getTargetOpcode()).getImplicitDefs();
+ unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
+ const unsigned *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs();
assert(ImpDefs && "Caller should check hasPhysRegDefs");
const unsigned *SUImpDefs =
- TII->get(SU->Node->getTargetOpcode()).getImplicitDefs();
+ TII->get(SU->Node->getMachineOpcode()).getImplicitDefs();
if (!SUImpDefs)
return false;
for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
MVT VT = N->getValueType(i);
if (VT == MVT::Flag || VT == MVT::Other)
continue;
+ if (!N->hasAnyUseOfValue(i))
+ continue;
unsigned Reg = ImpDefs[i - NumDefs];
for (;*SUImpDefs; ++SUImpDefs) {
unsigned SUReg = *SUImpDefs;
/// commutable, favor the one that's not commutable.
void BURegReductionPriorityQueue::AddPseudoTwoAddrDeps() {
for (unsigned i = 0, e = SUnits->size(); i != e; ++i) {
- SUnit *SU = (SUnit *)&((*SUnits)[i]);
+ SUnit *SU = &(*SUnits)[i];
if (!SU->isTwoAddress)
continue;
SDNode *Node = SU->Node;
- if (!Node || !Node->isTargetOpcode() || SU->FlaggedNodes.size() > 0)
+ if (!Node || !Node->isMachineOpcode() || SU->FlaggedNodes.size() > 0)
continue;
- unsigned Opc = Node->getTargetOpcode();
+ unsigned Opc = Node->getMachineOpcode();
const TargetInstrDesc &TID = TII->get(Opc);
unsigned NumRes = TID.getNumDefs();
unsigned NumOps = TID.getNumOperands() - NumRes;
for (unsigned j = 0; j != NumOps; ++j) {
if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) != -1) {
- SDNode *DU = SU->Node->getOperand(j).Val;
+ SDNode *DU = SU->Node->getOperand(j).getNode();
if (DU->getNodeId() == -1)
continue;
const SUnit *DUSU = &(*SUnits)[DU->getNodeId()];
// depth and height.
if (SuccSU->Height < SU->Height && (SU->Height - SuccSU->Height) > 1)
continue;
- if (!SuccSU->Node || !SuccSU->Node->isTargetOpcode())
+ if (!SuccSU->Node || !SuccSU->Node->isMachineOpcode())
continue;
// Don't constrain nodes with physical register defs if the
// predecessor can clobber them.
}
// Don't constraint extract_subreg / insert_subreg these may be
// coalesced away. We don't them close to their uses.
- unsigned SuccOpc = SuccSU->Node->getTargetOpcode();
+ unsigned SuccOpc = SuccSU->Node->getMachineOpcode();
if (SuccOpc == TargetInstrInfo::EXTRACT_SUBREG ||
SuccOpc == TargetInstrInfo::INSERT_SUBREG)
continue;
}
}
-/// CalcNodeSethiUllmanNumber - Priority is the Sethi Ullman number.
-/// Smaller number is the higher priority.
-unsigned BURegReductionPriorityQueue::
-CalcNodeSethiUllmanNumber(const SUnit *SU) {
- unsigned &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum];
- if (SethiUllmanNumber != 0)
- return SethiUllmanNumber;
-
- unsigned Extra = 0;
- for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
- I != E; ++I) {
- if (I->isCtrl) continue; // ignore chain preds
- SUnit *PredSU = I->Dep;
- unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU);
- if (PredSethiUllman > SethiUllmanNumber) {
- SethiUllmanNumber = PredSethiUllman;
- Extra = 0;
- } else if (PredSethiUllman == SethiUllmanNumber && !I->isCtrl)
- ++Extra;
- }
-
- SethiUllmanNumber += Extra;
-
- if (SethiUllmanNumber == 0)
- SethiUllmanNumber = 1;
-
- return SethiUllmanNumber;
-}
-
/// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all
/// scheduling units.
void BURegReductionPriorityQueue::CalculateSethiUllmanNumbers() {
SethiUllmanNumbers.assign(SUnits->size(), 0);
for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
- CalcNodeSethiUllmanNumber(&(*SUnits)[i]);
+ CalcNodeBUSethiUllmanNumber(&(*SUnits)[i], SethiUllmanNumbers);
+}
+void BURegReductionFastPriorityQueue::CalculateSethiUllmanNumbers() {
+ SethiUllmanNumbers.assign(SUnits->size(), 0);
+
+ for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
+ CalcNodeBUSethiUllmanNumber(&(*SUnits)[i], SethiUllmanNumbers);
}
/// LimitedSumOfUnscheduledPredsOfSuccs - Compute the sum of the unscheduled
unsigned Sum = 0;
for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
I != E; ++I) {
- SUnit *SuccSU = I->Dep;
+ const SUnit *SuccSU = I->Dep;
for (SUnit::const_pred_iterator II = SuccSU->Preds.begin(),
EE = SuccSU->Preds.end(); II != EE; ++II) {
SUnit *PredSU = II->Dep;
bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
unsigned LPriority = SPQ->getNodePriority(left);
unsigned RPriority = SPQ->getNodePriority(right);
- bool LIsTarget = left->Node && left->Node->isTargetOpcode();
- bool RIsTarget = right->Node && right->Node->isTargetOpcode();
+ bool LIsTarget = left->Node && left->Node->isMachineOpcode();
+ bool RIsTarget = right->Node && right->Node->isMachineOpcode();
bool LIsFloater = LIsTarget && left->NumPreds == 0;
bool RIsFloater = RIsTarget && right->NumPreds == 0;
unsigned LBonus = (LimitedSumOfUnscheduledPredsOfSuccs(left,1) == 1) ? 2 : 0;
return (left->NodeQueueId > right->NodeQueueId);
}
-/// CalcNodeSethiUllmanNumber - Priority is the Sethi Ullman number.
-/// Smaller number is the higher priority.
-unsigned TDRegReductionPriorityQueue::
-CalcNodeSethiUllmanNumber(const SUnit *SU) {
- unsigned &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum];
- if (SethiUllmanNumber != 0)
- return SethiUllmanNumber;
-
- unsigned Opc = SU->Node ? SU->Node->getOpcode() : 0;
- if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
- SethiUllmanNumber = 0xffff;
- else if (SU->NumSuccsLeft == 0)
- // If SU does not have a use, i.e. it doesn't produce a value that would
- // be consumed (e.g. store), then it terminates a chain of computation.
- // Give it a small SethiUllman number so it will be scheduled right before
- // its predecessors that it doesn't lengthen their live ranges.
- SethiUllmanNumber = 0;
- else if (SU->NumPredsLeft == 0 &&
- (Opc != ISD::CopyFromReg || isCopyFromLiveIn(SU)))
- SethiUllmanNumber = 0xffff;
- else {
- int Extra = 0;
- for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
- I != E; ++I) {
- if (I->isCtrl) continue; // ignore chain preds
- SUnit *PredSU = I->Dep;
- unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU);
- if (PredSethiUllman > SethiUllmanNumber) {
- SethiUllmanNumber = PredSethiUllman;
- Extra = 0;
- } else if (PredSethiUllman == SethiUllmanNumber && !I->isCtrl)
- ++Extra;
- }
-
- SethiUllmanNumber += Extra;
- }
-
- return SethiUllmanNumber;
-}
-
/// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all
/// scheduling units.
void TDRegReductionPriorityQueue::CalculateSethiUllmanNumbers() {
SethiUllmanNumbers.assign(SUnits->size(), 0);
for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
- CalcNodeSethiUllmanNumber(&(*SUnits)[i]);
+ CalcNodeTDSethiUllmanNumber(&(*SUnits)[i], SethiUllmanNumbers);
}
//===----------------------------------------------------------------------===//
SelectionDAG *DAG,
MachineBasicBlock *BB,
bool Fast) {
+ if (Fast)
+ return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true, true,
+ new BURegReductionFastPriorityQueue());
+
const TargetInstrInfo *TII = DAG->getTarget().getInstrInfo();
const TargetRegisterInfo *TRI = DAG->getTarget().getRegisterInfo();
- BURegReductionPriorityQueue *priorityQueue =
- new BURegReductionPriorityQueue(TII, TRI, Fast);
+ BURegReductionPriorityQueue *PQ = new BURegReductionPriorityQueue(TII, TRI);
- ScheduleDAGRRList * scheduleDAG =
- new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true, Fast,priorityQueue);
- priorityQueue->setScheduleDAG(scheduleDAG);
- return scheduleDAG;
+ ScheduleDAGRRList *SD =
+ new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(),true,false, PQ);
+ PQ->setScheduleDAG(SD);
+ return SD;
}
llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS,
MachineBasicBlock *BB,
bool Fast) {
return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), false, Fast,
- new TDRegReductionPriorityQueue());
+ new TDRegReductionPriorityQueue());
}
-
projects / oota-llvm.git / blobdiff