More constification of things. More comments added. No functionality

[oota-llvm.git] / lib / CodeGen / SelectionDAG / SelectionDAG.cpp

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 3ec60cde9d7cf909039830a945c21c4bd16982c5..eb3729c813f6ba17b7d6df43b6fb1aa19d0c6e44 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -176,6 +176,27 @@ bool ISD::isBuildVectorAllZeros(const SDNode *N) {
   return true;
 }
 
+/// isScalarToVector - Return true if the specified node is a
+/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low
+/// element is not an undef.
+bool ISD::isScalarToVector(const SDNode *N) {
+  if (N->getOpcode() == ISD::SCALAR_TO_VECTOR)
+    return true;
+
+  if (N->getOpcode() != ISD::BUILD_VECTOR)
+    return false;
+  if (N->getOperand(0).getOpcode() == ISD::UNDEF)
+    return false;
+  unsigned NumElems = N->getNumOperands();
+  for (unsigned i = 1; i < NumElems; ++i) {
+    SDOperand V = N->getOperand(i);
+    if (V.getOpcode() != ISD::UNDEF)
+      return false;
+  }
+  return true;
+}
+
+
 /// isDebugLabel - Return true if the specified node represents a debug
 /// label (i.e. ISD::LABEL or TargetInstrInfo::LABEL node and third operand
 /// is 0).
@@ -340,7 +361,7 @@ static void AddNodeIDNode(FoldingSetNodeID &ID, SDNode *N) {
   default: break;  // Normal nodes don't need extra info.
   case ISD::TargetConstant:
   case ISD::Constant:
-    ID.AddInteger(cast<ConstantSDNode>(N)->getValue());
+    ID.Add(cast<ConstantSDNode>(N)->getAPIntValue());
     break;
   case ISD::TargetConstantFP:
   case ISD::ConstantFP: {
@@ -1134,14 +1155,13 @@ void SelectionDAG::ComputeMaskedBits(SDOperand Op, const APInt &Mask,
                                      APInt &KnownZero, APInt &KnownOne,
                                      unsigned Depth) const {
   unsigned BitWidth = Mask.getBitWidth();
+  assert(BitWidth == MVT::getSizeInBits(Op.getValueType()) &&
+         "Mask size mismatches value type size!");
+
   KnownZero = KnownOne = APInt(BitWidth, 0);   // Don't know anything.
   if (Depth == 6 || Mask == 0)
     return;  // Limit search depth.
   
-  // The masks are not wide enough to represent this type!  Should use APInt.
-  if (Op.getValueType() == MVT::i128)
-    return;
-  
   APInt KnownZero2, KnownOne2;
 
   switch (Op.getOpcode()) {
@@ -1237,7 +1257,7 @@ void SelectionDAG::ComputeMaskedBits(SDOperand Op, const APInt &Mask,
       KnownZero = KnownZero.lshr(ShAmt);
       KnownOne  = KnownOne.lshr(ShAmt);
 
-      APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
+      APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask;
       KnownZero |= HighBits;  // High bits known zero.
     }
     return;
@@ -1248,8 +1268,8 @@ void SelectionDAG::ComputeMaskedBits(SDOperand Op, const APInt &Mask,
       APInt InDemandedMask = (Mask << ShAmt);
       // If any of the demanded bits are produced by the sign extension, we also
       // demand the input sign bit.
-      APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
-      if (!!(HighBits & Mask))
+      APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask;
+      if (HighBits.getBoolValue())
         InDemandedMask |= APInt::getSignBit(BitWidth);
       
       ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne,
@@ -1438,12 +1458,10 @@ void SelectionDAG::ComputeMaskedBits(SDOperand Op, const APInt &Mask,
     // We know that the top bits of C-X are clear if X contains less bits
     // than C (i.e. no wrap-around can happen).  For example, 20-X is
     // positive if we can prove that X is >= 0 and < 16.
-
-    // sign bit clear
     if (CLHS->getAPIntValue().isNonNegative()) {
       unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros();
       // NLZ can't be BitWidth with no sign bit
-      APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ);
+      APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1);
       ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero, KnownOne, Depth+1);
 
       // If all of the MaskV bits are known to be zero, then we know the output
@@ -1477,6 +1495,10 @@ void SelectionDAG::ComputeMaskedBits(SDOperand Op, const APInt &Mask,
 void SelectionDAG::ComputeMaskedBits(SDOperand Op, uint64_t Mask, 
                                      uint64_t &KnownZero, uint64_t &KnownOne,
                                      unsigned Depth) const {
+  // The masks are not wide enough to represent this type!  Should use APInt.
+  if (Op.getValueType() == MVT::i128)
+    return;
+  
   unsigned NumBits = MVT::getSizeInBits(Op.getValueType());
   APInt APIntMask(NumBits, Mask);
   APInt APIntKnownZero(NumBits, 0);
@@ -3791,6 +3813,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
       return "<<Unknown Target Node>>";
     }
    
+  case ISD::MEMBARRIER:    return "MemBarrier";
   case ISD::PCMARKER:      return "PCMarker";
   case ISD::READCYCLECOUNTER: return "ReadCycleCounter";
   case ISD::SRCVALUE:      return "SrcValue";