#include <iostream>
using namespace llvm;
-static cl::opt<bool>
-SplitPHICritEdges("split-phi-constant-crit-edges", cl::Hidden,
- cl::desc("Split critical edges for PHI values that are constants"));
-
-
#ifndef _NDEBUG
static cl::opt<bool>
ViewDAGs("view-isel-dags", cl::Hidden,
void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
//
- void visitBinary(User &I, unsigned Opcode);
+ void visitBinary(User &I, unsigned Opcode, bool isShift = false);
void visitAdd(User &I) { visitBinary(I, ISD::ADD); }
void visitSub(User &I);
void visitMul(User &I) { visitBinary(I, ISD::MUL); }
void visitAnd(User &I) { visitBinary(I, ISD::AND); }
void visitOr (User &I) { visitBinary(I, ISD::OR); }
void visitXor(User &I) { visitBinary(I, ISD::XOR); }
- void visitShl(User &I) { visitBinary(I, ISD::SHL); }
+ void visitShl(User &I) { visitBinary(I, ISD::SHL, true); }
void visitShr(User &I) {
- visitBinary(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);
+ visitBinary(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA, true);
}
void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc);
visitBinary(I, ISD::SUB);
}
-void SelectionDAGLowering::visitBinary(User &I, unsigned Opcode) {
+void SelectionDAGLowering::visitBinary(User &I, unsigned Opcode, bool isShift) {
SDOperand Op1 = getValue(I.getOperand(0));
SDOperand Op2 = getValue(I.getOperand(1));
- if (isa<ShiftInst>(I))
+ if (isShift)
Op2 = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), Op2);
setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
DAG.setRoot(Result.second);
}
+// InsertAtEndOfBasicBlock - This method should be implemented by targets that
+// mark instructions with the 'usesCustomDAGSchedInserter' flag. These
+// instructions are special in various ways, which require special support to
+// insert. The specified MachineInstr is created but not inserted into any
+// basic blocks, and the scheduler passes ownership of it to this method.
+MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
+ MachineBasicBlock *MBB) {
+ std::cerr << "If a target marks an instruction with "
+ "'usesCustomDAGSchedInserter', it must implement "
+ "TargetLowering::InsertAtEndOfBasicBlock!\n";
+ abort();
+ return 0;
+}
+
SDOperand TargetLowering::LowerVAStart(SDOperand Chain,
SDOperand VAListP, Value *VAListV,
SelectionDAG &DAG) {
}
void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
- if (!SplitPHICritEdges)
- AU.setPreservesAll();
+ // FIXME: we only modify the CFG to split critical edges. This
+ // updates dom and loop info.
}
// First pass, split all critical edges for PHI nodes with incoming values
// that are constants, this way the load of the constant into a vreg will not
// be placed into MBBs that are used some other way.
- if (SplitPHICritEdges)
- for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
- PHINode *PN;
- for (BasicBlock::iterator BBI = BB->begin();
- (PN = dyn_cast<PHINode>(BBI)); ++BBI)
- for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
- if (isa<Constant>(PN->getIncomingValue(i)))
- SplitCriticalEdge(PN->getIncomingBlock(i), BB);
- }
+ for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
+ PHINode *PN;
+ for (BasicBlock::iterator BBI = BB->begin();
+ (PN = dyn_cast<PHINode>(BBI)); ++BBI)
+ for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
+ if (isa<Constant>(PN->getIncomingValue(i)))
+ SplitCriticalEdge(PN->getIncomingBlock(i), BB);
+ }
FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
AI != E; ++AI,++a)
if (!AI->use_empty()) {
SDL.setValue(AI, Args[a]);
- SDOperand Copy =
- CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
- UnorderedChains.push_back(Copy);
+
+ if (0 && IsOnlyUsedInOneBasicBlock(AI) == F.begin()) {
+ // Only used in the entry block, no need to copy it to a vreg for
+ // other blocks.
+ } else {
+ SDOperand Copy =
+ CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
+ UnorderedChains.push_back(Copy);
+ }
}
} else {
// Otherwise, if any argument is only accessed in a single basic block,
DEBUG(std::cerr << "Legalized selection DAG:\n");
DEBUG(DAG.dump());
+ if (ViewDAGs) DAG.viewGraph();
+
// Third, instruction select all of the operations to machine code, adding the
// code to the MachineBasicBlock.
InstructionSelectBasicBlock(DAG);
- if (ViewDAGs) DAG.viewGraph();
-
DEBUG(std::cerr << "Selected machine code:\n");
DEBUG(BB->dump());