//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This implements the SelectionDAGISel class.
#define DEBUG_TYPE "isel"
#include "llvm/CodeGen/SelectionDAGISel.h"
+#include "llvm/CallingConv.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
+#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include <map>
unsigned MakeReg(MVT::ValueType VT) {
return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
}
-
+
unsigned CreateRegForValue(const Value *V) {
MVT::ValueType VT = TLI.getValueType(V->getType());
// The common case is that we will only create one register for this
// If we are promoting this value, pick the next largest supported type.
return MakeReg(TLI.getTypeToTransformTo(VT));
}
-
+
// If this value is represented with multiple target registers, make sure
// to create enough consequtive registers of the right (smaller) type.
unsigned NT = VT-1; // Find the type to use.
while (TLI.getNumElements((MVT::ValueType)NT) != 1)
--NT;
-
+
unsigned R = MakeReg((MVT::ValueType)NT);
for (unsigned i = 1; i != NV; ++i)
MakeReg((MVT::ValueType)NT);
return R;
}
-
+
unsigned InitializeRegForValue(const Value *V) {
unsigned &R = ValueMap[V];
assert(R == 0 && "Already initialized this value register!");
}
FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
- Function &fn, MachineFunction &mf)
+ Function &fn, MachineFunction &mf)
: TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
// Initialize the mapping of values to registers. This is only set up for
// instruction values that are used outside of the block that defines
// them.
- for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end(); AI != E; ++AI)
+ for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
+ AI != E; ++AI)
InitializeRegForValue(AI);
Function::iterator BB = Fn.begin(), E = Fn.end();
const Type *Ty = AI->getAllocatedType();
uint64_t TySize = TLI.getTargetData().getTypeSize(Ty);
unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
+
+ // If the alignment of the value is smaller than the size of the value,
+ // and if the size of the value is particularly small (<= 8 bytes),
+ // round up to the size of the value for potentially better performance.
+ //
+ // FIXME: This could be made better with a preferred alignment hook in
+ // TargetData. It serves primarily to 8-byte align doubles for X86.
+ if (Align < TySize && TySize <= 8) Align = TySize;
+
TySize *= CUI->getValue(); // Get total allocated size.
StaticAllocaMap[AI] =
MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
FunctionLoweringInfo &FuncInfo;
SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
- FunctionLoweringInfo &funcinfo)
+ FunctionLoweringInfo &funcinfo)
: TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
FuncInfo(funcinfo) {
}
SDOperand getRoot() {
if (PendingLoads.empty())
return DAG.getRoot();
-
+
if (PendingLoads.size() == 1) {
SDOperand Root = PendingLoads[0];
DAG.setRoot(Root);
} else if (isa<ConstantPointerNull>(C)) {
return N = DAG.getConstant(0, TLI.getPointerTy());
} else if (isa<UndefValue>(C)) {
- /// FIXME: Implement UNDEFVALUE better.
- if (MVT::isInteger(VT))
- return N = DAG.getConstant(0, VT);
- else if (MVT::isFloatingPoint(VT))
- return N = DAG.getConstantFP(0, VT);
- else
- assert(0 && "Unknown value type!");
-
+ return N = DAG.getNode(ISD::UNDEF, VT);
} else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
return N = DAG.getConstantFP(CFP->getValue(), VT);
} else {
FuncInfo.ValueMap.find(V);
assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
- return N = DAG.getCopyFromReg(VMI->second, VT, DAG.getEntryNode());
+ unsigned InReg = VMI->second;
+
+ // If this type is not legal, make it so now.
+ MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
+
+ N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
+ if (DestVT < VT) {
+ // Source must be expanded. This input value is actually coming from the
+ // register pair VMI->second and VMI->second+1.
+ N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
+ DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
+ } else {
+ if (DestVT > VT) { // Promotion case
+ if (MVT::isFloatingPoint(VT))
+ N = DAG.getNode(ISD::FP_ROUND, VT, N);
+ else
+ N = DAG.getNode(ISD::TRUNCATE, VT, N);
+ }
+ }
+
+ return N;
}
const SDOperand &setValue(const Value *V, SDOperand NewN) {
void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
//
- void visitBinary(User &I, unsigned Opcode);
+ void visitBinary(User &I, unsigned Opcode, bool isShift = false);
void visitAdd(User &I) { visitBinary(I, ISD::ADD); }
- void visitSub(User &I) { visitBinary(I, ISD::SUB); }
+ void visitSub(User &I);
void visitMul(User &I) { visitBinary(I, ISD::MUL); }
void visitDiv(User &I) {
visitBinary(I, I.getType()->isUnsigned() ? ISD::UDIV : ISD::SDIV);
void visitAnd(User &I) { visitBinary(I, ISD::AND); }
void visitOr (User &I) { visitBinary(I, ISD::OR); }
void visitXor(User &I) { visitBinary(I, ISD::XOR); }
- void visitShl(User &I) { visitBinary(I, ISD::SHL); }
+ void visitShl(User &I) { visitBinary(I, ISD::SHL, true); }
void visitShr(User &I) {
- visitBinary(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);
+ visitBinary(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA, true);
}
void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc);
void visitCall(CallInst &I);
void visitVAStart(CallInst &I);
- void visitVANext(VANextInst &I);
void visitVAArg(VAArgInst &I);
void visitVAEnd(CallInst &I);
void visitVACopy(CallInst &I);
}
SDOperand Op1 = getValue(I.getOperand(0));
+ MVT::ValueType TmpVT;
+
switch (Op1.getValueType()) {
default: assert(0 && "Unknown value type!");
case MVT::i1:
case MVT::i8:
case MVT::i16:
- // Extend integer types to 32-bits.
+ case MVT::i32:
+ // If this is a machine where 32-bits is legal or expanded, promote to
+ // 32-bits, otherwise, promote to 64-bits.
+ if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
+ TmpVT = TLI.getTypeToTransformTo(MVT::i32);
+ else
+ TmpVT = MVT::i32;
+
+ // Extend integer types to result type.
if (I.getOperand(0)->getType()->isSigned())
- Op1 = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Op1);
+ Op1 = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, Op1);
else
- Op1 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op1);
+ Op1 = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, Op1);
break;
case MVT::f32:
- // Extend float to double.
- Op1 = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Op1);
- break;
- case MVT::i32:
case MVT::i64:
case MVT::f64:
break; // No extension needed!
void SelectionDAGLowering::visitBr(BranchInst &I) {
// Update machine-CFG edges.
MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
- CurMBB->addSuccessor(Succ0MBB);
// Figure out which block is immediately after the current one.
MachineBasicBlock *NextBlock = 0;
// If this is not a fall-through branch, emit the branch.
if (Succ0MBB != NextBlock)
DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
- DAG.getBasicBlock(Succ0MBB)));
+ DAG.getBasicBlock(Succ0MBB)));
} else {
MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
- CurMBB->addSuccessor(Succ1MBB);
SDOperand Cond = getValue(I.getCondition());
-
if (Succ1MBB == NextBlock) {
// If the condition is false, fall through. This means we should branch
// if the condition is true to Succ #0.
DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
- Cond, DAG.getBasicBlock(Succ0MBB)));
+ Cond, DAG.getBasicBlock(Succ0MBB)));
} else if (Succ0MBB == NextBlock) {
// If the condition is true, fall through. This means we should branch if
// the condition is false to Succ #1. Invert the condition first.
SDOperand True = DAG.getConstant(1, Cond.getValueType());
Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
- Cond, DAG.getBasicBlock(Succ1MBB)));
+ Cond, DAG.getBasicBlock(Succ1MBB)));
} else {
- // Neither edge is a fall through. If the comparison is true, jump to
- // Succ#0, otherwise branch unconditionally to succ #1.
- DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
- Cond, DAG.getBasicBlock(Succ0MBB)));
- DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
- DAG.getBasicBlock(Succ1MBB)));
+ std::vector<SDOperand> Ops;
+ Ops.push_back(getRoot());
+ Ops.push_back(Cond);
+ Ops.push_back(DAG.getBasicBlock(Succ0MBB));
+ Ops.push_back(DAG.getBasicBlock(Succ1MBB));
+ DAG.setRoot(DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops));
}
}
}
-void SelectionDAGLowering::visitBinary(User &I, unsigned Opcode) {
+void SelectionDAGLowering::visitSub(User &I) {
+ // -0.0 - X --> fneg
+ if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
+ if (CFP->isExactlyValue(-0.0)) {
+ SDOperand Op2 = getValue(I.getOperand(1));
+ setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
+ return;
+ }
+
+ visitBinary(I, ISD::SUB);
+}
+
+void SelectionDAGLowering::visitBinary(User &I, unsigned Opcode, bool isShift) {
SDOperand Op1 = getValue(I.getOperand(0));
SDOperand Op2 = getValue(I.getOperand(1));
- if (isa<ShiftInst>(I))
+ if (isShift)
Op2 = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), Op2);
setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
ISD::CondCode Opcode = SignedOpcode;
if (I.getOperand(0)->getType()->isUnsigned())
Opcode = UnsignedOpcode;
- setValue(&I, DAG.getSetCC(Opcode, MVT::i1, Op1, Op2));
+ setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
}
void SelectionDAGLowering::visitSelect(User &I) {
if (N.getValueType() == DestTy) {
setValue(&I, N); // noop cast.
+ } else if (DestTy == MVT::i1) {
+ // Cast to bool is a comparison against zero, not truncation to zero.
+ SDOperand Zero = isInteger(SrcTy) ? DAG.getConstant(0, N.getValueType()) :
+ DAG.getConstantFP(0.0, N.getValueType());
+ setValue(&I, DAG.getSetCC(MVT::i1, N, Zero, ISD::SETNE));
} else if (isInteger(SrcTy)) {
if (isInteger(DestTy)) { // Int -> Int cast
if (DestTy < SrcTy) // Truncating cast?
// N = N + Offset
uint64_t Offset = TD.getStructLayout(StTy)->MemberOffsets[Field];
N = DAG.getNode(ISD::ADD, N.getValueType(), N,
- getIntPtrConstant(Offset));
+ getIntPtrConstant(Offset));
}
Ty = StTy->getElementType(Field);
} else {
IdxN = DAG.getNode(ISD::TRUNCATE, Scale.getValueType(), IdxN);
IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
-
N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
}
}
getIntPtrConstant(~(uint64_t)(StackAlign-1)));
}
- SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, AllocSize.getValueType(),
- getRoot(), AllocSize,
- getIntPtrConstant(Align));
+ std::vector<MVT::ValueType> VTs;
+ VTs.push_back(AllocSize.getValueType());
+ VTs.push_back(MVT::Other);
+ std::vector<SDOperand> Ops;
+ Ops.push_back(getRoot());
+ Ops.push_back(AllocSize);
+ Ops.push_back(getIntPtrConstant(Align));
+ SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops);
DAG.setRoot(setValue(&I, DSA).getValue(1));
// Inform the Frame Information that we have just allocated a variable-sized
void SelectionDAGLowering::visitLoad(LoadInst &I) {
SDOperand Ptr = getValue(I.getOperand(0));
-
+
SDOperand Root;
if (I.isVolatile())
Root = getRoot();
Root = DAG.getRoot();
}
- SDOperand L = DAG.getLoad(TLI.getValueType(I.getType()), Root, Ptr);
+ SDOperand L = DAG.getLoad(TLI.getValueType(I.getType()), Root, Ptr,
+ DAG.getSrcValue(I.getOperand(0)));
setValue(&I, L);
if (I.isVolatile())
Value *SrcV = I.getOperand(0);
SDOperand Src = getValue(SrcV);
SDOperand Ptr = getValue(I.getOperand(1));
- DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr));
+ DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr,
+ DAG.getSrcValue(I.getOperand(1))));
}
void SelectionDAGLowering::visitCall(CallInst &I) {
const char *RenameFn = 0;
+ SDOperand Tmp;
if (Function *F = I.getCalledFunction())
- switch (F->getIntrinsicID()) {
- case 0: break; // Not an intrinsic.
- case Intrinsic::vastart: visitVAStart(I); return;
- case Intrinsic::vaend: visitVAEnd(I); return;
- case Intrinsic::vacopy: visitVACopy(I); return;
- case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return;
- case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return;
- default:
- // FIXME: IMPLEMENT THESE.
- // readport, writeport, readio, writeio
- assert(0 && "This intrinsic is not implemented yet!");
- return;
- case Intrinsic::setjmp: RenameFn = "setjmp"; break;
- case Intrinsic::longjmp: RenameFn = "longjmp"; break;
- case Intrinsic::memcpy: visitMemIntrinsic(I, ISD::MEMCPY); return;
- case Intrinsic::memset: visitMemIntrinsic(I, ISD::MEMSET); return;
- case Intrinsic::memmove: visitMemIntrinsic(I, ISD::MEMMOVE); return;
-
- case Intrinsic::isunordered:
- setValue(&I, DAG.getSetCC(ISD::SETUO, MVT::i1, getValue(I.getOperand(1)),
+ if (F->isExternal())
+ switch (F->getIntrinsicID()) {
+ case 0: // Not an LLVM intrinsic.
+ if (F->getName() == "fabs" || F->getName() == "fabsf") {
+ if (I.getNumOperands() == 2 && // Basic sanity checks.
+ I.getOperand(1)->getType()->isFloatingPoint() &&
+ I.getType() == I.getOperand(1)->getType()) {
+ Tmp = getValue(I.getOperand(1));
+ setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
+ return;
+ }
+ }
+ else if (F->getName() == "sin" || F->getName() == "sinf") {
+ if (I.getNumOperands() == 2 && // Basic sanity checks.
+ I.getOperand(1)->getType()->isFloatingPoint() &&
+ I.getType() == I.getOperand(1)->getType()) {
+ Tmp = getValue(I.getOperand(1));
+ setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
+ return;
+ }
+ }
+ else if (F->getName() == "cos" || F->getName() == "cosf") {
+ if (I.getNumOperands() == 2 && // Basic sanity checks.
+ I.getOperand(1)->getType()->isFloatingPoint() &&
+ I.getType() == I.getOperand(1)->getType()) {
+ Tmp = getValue(I.getOperand(1));
+ setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
+ return;
+ }
+ }
+ break;
+ case Intrinsic::vastart: visitVAStart(I); return;
+ case Intrinsic::vaend: visitVAEnd(I); return;
+ case Intrinsic::vacopy: visitVACopy(I); return;
+ case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return;
+ case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return;
+
+ case Intrinsic::setjmp: RenameFn = "setjmp"; break;
+ case Intrinsic::longjmp: RenameFn = "longjmp"; break;
+ case Intrinsic::memcpy: visitMemIntrinsic(I, ISD::MEMCPY); return;
+ case Intrinsic::memset: visitMemIntrinsic(I, ISD::MEMSET); return;
+ case Intrinsic::memmove: visitMemIntrinsic(I, ISD::MEMMOVE); return;
+
+ case Intrinsic::readport:
+ case Intrinsic::readio: {
+ std::vector<MVT::ValueType> VTs;
+ VTs.push_back(TLI.getValueType(I.getType()));
+ VTs.push_back(MVT::Other);
+ std::vector<SDOperand> Ops;
+ Ops.push_back(getRoot());
+ Ops.push_back(getValue(I.getOperand(1)));
+ Tmp = DAG.getNode(F->getIntrinsicID() == Intrinsic::readport ?
+ ISD::READPORT : ISD::READIO, VTs, Ops);
+
+ setValue(&I, Tmp);
+ DAG.setRoot(Tmp.getValue(1));
+ return;
+ }
+ case Intrinsic::writeport:
+ case Intrinsic::writeio:
+ DAG.setRoot(DAG.getNode(F->getIntrinsicID() == Intrinsic::writeport ?
+ ISD::WRITEPORT : ISD::WRITEIO, MVT::Other,
+ getRoot(), getValue(I.getOperand(1)),
getValue(I.getOperand(2))));
- return;
- }
-
+ return;
+ case Intrinsic::dbg_stoppoint:
+ case Intrinsic::dbg_region_start:
+ case Intrinsic::dbg_region_end:
+ case Intrinsic::dbg_func_start:
+ case Intrinsic::dbg_declare:
+ if (I.getType() != Type::VoidTy)
+ setValue(&I, DAG.getNode(ISD::UNDEF, TLI.getValueType(I.getType())));
+ return;
+
+ case Intrinsic::isunordered:
+ setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)),
+ getValue(I.getOperand(2)), ISD::SETUO));
+ return;
+
+ case Intrinsic::sqrt:
+ setValue(&I, DAG.getNode(ISD::FSQRT,
+ getValue(I.getOperand(1)).getValueType(),
+ getValue(I.getOperand(1))));
+ return;
+
+ case Intrinsic::pcmarker:
+ Tmp = getValue(I.getOperand(1));
+ DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
+ return;
+ case Intrinsic::cttz:
+ setValue(&I, DAG.getNode(ISD::CTTZ,
+ getValue(I.getOperand(1)).getValueType(),
+ getValue(I.getOperand(1))));
+ return;
+ case Intrinsic::ctlz:
+ setValue(&I, DAG.getNode(ISD::CTLZ,
+ getValue(I.getOperand(1)).getValueType(),
+ getValue(I.getOperand(1))));
+ return;
+ case Intrinsic::ctpop:
+ setValue(&I, DAG.getNode(ISD::CTPOP,
+ getValue(I.getOperand(1)).getValueType(),
+ getValue(I.getOperand(1))));
+ return;
+ default:
+ std::cerr << I;
+ assert(0 && "This intrinsic is not implemented yet!");
+ return;
+ }
+
SDOperand Callee;
if (!RenameFn)
Callee = getValue(I.getOperand(0));
else
Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
std::vector<std::pair<SDOperand, const Type*> > Args;
-
+
for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
Value *Arg = I.getOperand(i);
SDOperand ArgNode = getValue(Arg);
Args.push_back(std::make_pair(ArgNode, Arg->getType()));
}
-
+
const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType());
const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
-
+
std::pair<SDOperand,SDOperand> Result =
- TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), Callee, Args, DAG);
+ TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), I.getCallingConv(),
+ I.isTailCall(), Callee, Args, DAG);
if (I.getType() != Type::VoidTy)
setValue(&I, Result.first);
DAG.setRoot(Result.second);
Args.push_back(std::make_pair(Src, TLI.getTargetData().getIntPtrType()));
std::pair<SDOperand,SDOperand> Result =
- TLI.LowerCallTo(getRoot(), I.getType(), false,
+ TLI.LowerCallTo(getRoot(), I.getType(), false, CallingConv::C, true,
DAG.getExternalSymbol("malloc", IntPtr),
Args, DAG);
setValue(&I, Result.first); // Pointers always fit in registers
TLI.getTargetData().getIntPtrType()));
MVT::ValueType IntPtr = TLI.getPointerTy();
std::pair<SDOperand,SDOperand> Result =
- TLI.LowerCallTo(getRoot(), Type::VoidTy, false,
+ TLI.LowerCallTo(getRoot(), Type::VoidTy, false, CallingConv::C, true,
DAG.getExternalSymbol("free", IntPtr), Args, DAG);
DAG.setRoot(Result.second);
}
-std::pair<SDOperand, SDOperand>
-TargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG) {
+// InsertAtEndOfBasicBlock - This method should be implemented by targets that
+// mark instructions with the 'usesCustomDAGSchedInserter' flag. These
+// instructions are special in various ways, which require special support to
+// insert. The specified MachineInstr is created but not inserted into any
+// basic blocks, and the scheduler passes ownership of it to this method.
+MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
+ MachineBasicBlock *MBB) {
+ std::cerr << "If a target marks an instruction with "
+ "'usesCustomDAGSchedInserter', it must implement "
+ "TargetLowering::InsertAtEndOfBasicBlock!\n";
+ abort();
+ return 0;
+}
+
+SDOperand TargetLowering::LowerVAStart(SDOperand Chain,
+ SDOperand VAListP, Value *VAListV,
+ SelectionDAG &DAG) {
// We have no sane default behavior, just emit a useful error message and bail
// out.
std::cerr << "Variable arguments handling not implemented on this target!\n";
abort();
- return std::make_pair(SDOperand(), SDOperand());
+ return SDOperand();
}
-SDOperand TargetLowering::LowerVAEnd(SDOperand Chain, SDOperand L,
+SDOperand TargetLowering::LowerVAEnd(SDOperand Chain, SDOperand LP, Value *LV,
SelectionDAG &DAG) {
// Default to a noop.
return Chain;
}
-std::pair<SDOperand,SDOperand>
-TargetLowering::LowerVACopy(SDOperand Chain, SDOperand L, SelectionDAG &DAG) {
- // Default to returning the input list.
- return std::make_pair(L, Chain);
+SDOperand TargetLowering::LowerVACopy(SDOperand Chain,
+ SDOperand SrcP, Value *SrcV,
+ SDOperand DestP, Value *DestV,
+ SelectionDAG &DAG) {
+ // Default to copying the input list.
+ SDOperand Val = DAG.getLoad(getPointerTy(), Chain,
+ SrcP, DAG.getSrcValue(SrcV));
+ SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
+ Val, DestP, DAG.getSrcValue(DestV));
+ return Result;
}
std::pair<SDOperand,SDOperand>
-TargetLowering::LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
- const Type *ArgTy, SelectionDAG &DAG) {
+TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
+ const Type *ArgTy, SelectionDAG &DAG) {
// We have no sane default behavior, just emit a useful error message and bail
// out.
std::cerr << "Variable arguments handling not implemented on this target!\n";
void SelectionDAGLowering::visitVAStart(CallInst &I) {
- std::pair<SDOperand,SDOperand> Result = TLI.LowerVAStart(getRoot(), DAG);
- setValue(&I, Result.first);
- DAG.setRoot(Result.second);
+ DAG.setRoot(TLI.LowerVAStart(getRoot(), getValue(I.getOperand(1)),
+ I.getOperand(1), DAG));
}
void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
std::pair<SDOperand,SDOperand> Result =
- TLI.LowerVAArgNext(false, getRoot(), getValue(I.getOperand(0)),
- I.getType(), DAG);
- setValue(&I, Result.first);
- DAG.setRoot(Result.second);
-}
-
-void SelectionDAGLowering::visitVANext(VANextInst &I) {
- std::pair<SDOperand,SDOperand> Result =
- TLI.LowerVAArgNext(true, getRoot(), getValue(I.getOperand(0)),
- I.getArgType(), DAG);
+ TLI.LowerVAArg(getRoot(), getValue(I.getOperand(0)), I.getOperand(0),
+ I.getType(), DAG);
setValue(&I, Result.first);
DAG.setRoot(Result.second);
}
void SelectionDAGLowering::visitVAEnd(CallInst &I) {
- DAG.setRoot(TLI.LowerVAEnd(getRoot(), getValue(I.getOperand(1)), DAG));
+ DAG.setRoot(TLI.LowerVAEnd(getRoot(), getValue(I.getOperand(1)),
+ I.getOperand(1), DAG));
}
void SelectionDAGLowering::visitVACopy(CallInst &I) {
- std::pair<SDOperand,SDOperand> Result =
- TLI.LowerVACopy(getRoot(), getValue(I.getOperand(1)), DAG);
- setValue(&I, Result.first);
- DAG.setRoot(Result.second);
+ SDOperand Result =
+ TLI.LowerVACopy(getRoot(), getValue(I.getOperand(2)), I.getOperand(2),
+ getValue(I.getOperand(1)), I.getOperand(1), DAG);
+ DAG.setRoot(Result);
}
return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain);
}
-SDOperand TargetLowering::LowerOperation(SDOperand Op) {
+SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
assert(0 && "LowerOperation not implemented for this target!");
abort();
return SDOperand();
return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
}
+void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
+ // FIXME: we only modify the CFG to split critical edges. This
+ // updates dom and loop info.
+}
bool SelectionDAGISel::runOnFunction(Function &Fn) {
RegMap = MF.getSSARegMap();
DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n");
+ // First pass, split all critical edges for PHI nodes with incoming values
+ // that are constants, this way the load of the constant into a vreg will not
+ // be placed into MBBs that are used some other way.
+ for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
+ PHINode *PN;
+ for (BasicBlock::iterator BBI = BB->begin();
+ (PN = dyn_cast<PHINode>(BBI)); ++BBI)
+ for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
+ if (isa<Constant>(PN->getIncomingValue(i)))
+ SplitCriticalEdge(PN->getIncomingBlock(i), BB);
+ }
+
FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
SelectBasicBlock(I, MF, FuncInfo);
-
+
return true;
}
SDOperand SelectionDAGISel::
CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
- SelectionDAG &DAG = SDL.DAG;
SDOperand Op = SDL.getValue(V);
assert((Op.getOpcode() != ISD::CopyFromReg ||
- cast<RegSDNode>(Op)->getReg() != Reg) &&
+ cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
"Copy from a reg to the same reg!");
- return DAG.getCopyToReg(SDL.getRoot(), Op, Reg);
+
+ // If this type is not legal, we must make sure to not create an invalid
+ // register use.
+ MVT::ValueType SrcVT = Op.getValueType();
+ MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT);
+ SelectionDAG &DAG = SDL.DAG;
+ if (SrcVT == DestVT) {
+ return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
+ } else if (SrcVT < DestVT) {
+ // The src value is promoted to the register.
+ if (MVT::isFloatingPoint(SrcVT))
+ Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op);
+ else
+ Op = DAG.getNode(ISD::ZERO_EXTEND, DestVT, Op);
+ return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
+ } else {
+ // The src value is expanded into multiple registers.
+ SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
+ Op, DAG.getConstant(0, MVT::i32));
+ SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
+ Op, DAG.getConstant(1, MVT::i32));
+ Op = DAG.getCopyToReg(SDL.getRoot(), Reg, Lo);
+ return DAG.getCopyToReg(Op, Reg+1, Hi);
+ }
}
/// IsOnlyUsedInOneBasicBlock - If the specified argument is only used in a
// anything special.
if (OldRoot != SDL.DAG.getRoot()) {
unsigned a = 0;
- for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); AI != E; ++AI,++a)
+ for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
+ AI != E; ++AI,++a)
if (!AI->use_empty()) {
SDL.setValue(AI, Args[a]);
- SDOperand Copy =
- CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
- UnorderedChains.push_back(Copy);
+
+ if (0 && IsOnlyUsedInOneBasicBlock(AI) == F.begin()) {
+ // Only used in the entry block, no need to copy it to a vreg for
+ // other blocks.
+ } else {
+ SDOperand Copy =
+ CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
+ UnorderedChains.push_back(Copy);
+ }
}
} else {
// Otherwise, if any argument is only accessed in a single basic block,
// emit that argument only to that basic block.
unsigned a = 0;
- for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); AI != E; ++AI,++a)
+ for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
+ AI != E; ++AI,++a)
if (!AI->use_empty()) {
if (BasicBlock *BBU = IsOnlyUsedInOneBasicBlock(AI)) {
FuncInfo.BlockLocalArguments.insert(std::make_pair(BBU,
std::make_pair(AI, a)));
} else {
SDL.setValue(AI, Args[a]);
- SDOperand Copy =
+ SDOperand Copy =
CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
UnorderedChains.push_back(Copy);
}
}
}
+
+ EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
}
// See if there are any block-local arguments that need to be emitted in this
if (BLAI != FuncInfo.BlockLocalArguments.end() && BLAI->first == BB) {
// Lower the arguments into this block.
std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
-
+
// Set up the value mapping for the local arguments.
for (; BLAI != FuncInfo.BlockLocalArguments.end() && BLAI->first == BB;
++BLAI)
SDL.setValue(BLAI->second.first, Args[BLAI->second.second]);
-
+
// Any dead arguments will just be ignored here.
}
}
SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
std::vector<SDOperand> UnorderedChains;
-
+
// Lower any arguments needed in this block.
LowerArguments(LLVMBB, SDL, UnorderedChains);
// directly add them, because expansion might result in multiple MBB's for one
// BB. As such, the start of the BB might correspond to a different MBB than
// the end.
- //
+ //
// Emit constants only once even if used by multiple PHI nodes.
std::map<Constant*, unsigned> ConstantsOut;
} else {
Reg = FuncInfo.ValueMap[PHIOp];
if (Reg == 0) {
- assert(isa<AllocaInst>(PHIOp) &&
+ assert(isa<AllocaInst>(PHIOp) &&
FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
"Didn't codegen value into a register!??");
Reg = FuncInfo.CreateRegForValue(PHIOp);
CopyValueToVirtualRegister(SDL, PHIOp, Reg));
}
}
-
+
// Remember that this register needs to added to the machine PHI node as
// the input for this MBB.
unsigned NumElements =
DEBUG(std::cerr << "Legalized selection DAG:\n");
DEBUG(DAG.dump());
- // Finally, instruction select all of the operations to machine code, adding
- // the code to the MachineBasicBlock.
- InstructionSelectBasicBlock(DAG);
-
if (ViewDAGs) DAG.viewGraph();
+ // Third, instruction select all of the operations to machine code, adding the
+ // code to the MachineBasicBlock.
+ InstructionSelectBasicBlock(DAG);
+
DEBUG(std::cerr << "Selected machine code:\n");
DEBUG(BB->dump());
- // Finally, now that we know what the last MBB the LLVM BB expanded is, update
+ // Next, now that we know what the last MBB the LLVM BB expanded is, update
// PHI nodes in successors.
for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
MachineInstr *PHI = PHINodesToUpdate[i].first;
PHI->addRegOperand(PHINodesToUpdate[i].second);
PHI->addMachineBasicBlockOperand(BB);
}
+
+ // Finally, add the CFG edges from the last selected MBB to the successor
+ // MBBs.
+ TerminatorInst *TI = LLVMBB->getTerminator();
+ for (unsigned i = 0, e = TI->getNumSuccessors(); i != e; ++i) {
+ MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[TI->getSuccessor(i)];
+ BB->addSuccessor(Succ0MBB);
+ }
}
projects / oota-llvm.git / blobdiff