#include "llvm/Support/MathExtras.h"
using namespace llvm;
+/// InitLibcallNames - Set default libcall names.
+///
+static void InitLibcallNames(const char **Names) {
+ Names[RTLIB::SHL_I32] = "__ashlsi3";
+ Names[RTLIB::SHL_I64] = "__ashldi3";
+ Names[RTLIB::SRL_I32] = "__lshrsi3";
+ Names[RTLIB::SRL_I64] = "__lshrdi3";
+ Names[RTLIB::SRA_I32] = "__ashrsi3";
+ Names[RTLIB::SRA_I64] = "__ashrdi3";
+ Names[RTLIB::MUL_I32] = "__mulsi3";
+ Names[RTLIB::MUL_I64] = "__muldi3";
+ Names[RTLIB::SDIV_I32] = "__divsi3";
+ Names[RTLIB::SDIV_I64] = "__divdi3";
+ Names[RTLIB::UDIV_I32] = "__udivsi3";
+ Names[RTLIB::UDIV_I64] = "__udivdi3";
+ Names[RTLIB::SREM_I32] = "__modsi3";
+ Names[RTLIB::SREM_I64] = "__moddi3";
+ Names[RTLIB::UREM_I32] = "__umodsi3";
+ Names[RTLIB::UREM_I64] = "__umoddi3";
+ Names[RTLIB::NEG_I32] = "__negsi2";
+ Names[RTLIB::NEG_I64] = "__negdi2";
+ Names[RTLIB::ADD_F32] = "__addsf3";
+ Names[RTLIB::ADD_F64] = "__adddf3";
+ Names[RTLIB::SUB_F32] = "__subsf3";
+ Names[RTLIB::SUB_F64] = "__subdf3";
+ Names[RTLIB::MUL_F32] = "__mulsf3";
+ Names[RTLIB::MUL_F64] = "__muldf3";
+ Names[RTLIB::DIV_F32] = "__divsf3";
+ Names[RTLIB::DIV_F64] = "__divdf3";
+ Names[RTLIB::REM_F32] = "fmodf";
+ Names[RTLIB::REM_F64] = "fmod";
+ Names[RTLIB::NEG_F32] = "__negsf2";
+ Names[RTLIB::NEG_F64] = "__negdf2";
+ Names[RTLIB::POWI_F32] = "__powisf2";
+ Names[RTLIB::POWI_F64] = "__powidf2";
+ Names[RTLIB::SQRT_F32] = "sqrtf";
+ Names[RTLIB::SQRT_F64] = "sqrt";
+ Names[RTLIB::SIN_F32] = "sinf";
+ Names[RTLIB::SIN_F64] = "sin";
+ Names[RTLIB::COS_F32] = "cosf";
+ Names[RTLIB::COS_F64] = "cos";
+ Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
+ Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
+ Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
+ Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
+ Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
+ Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
+ Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
+ Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
+ Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
+ Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
+ Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
+ Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
+ Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
+ Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
+ Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
+ Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
+ Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
+ Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
+ Names[RTLIB::OEQ_F32] = "__eqsf2";
+ Names[RTLIB::OEQ_F64] = "__eqdf2";
+ Names[RTLIB::UNE_F32] = "__nesf2";
+ Names[RTLIB::UNE_F64] = "__nedf2";
+ Names[RTLIB::OGE_F32] = "__gesf2";
+ Names[RTLIB::OGE_F64] = "__gedf2";
+ Names[RTLIB::OLT_F32] = "__ltsf2";
+ Names[RTLIB::OLT_F64] = "__ltdf2";
+ Names[RTLIB::OLE_F32] = "__lesf2";
+ Names[RTLIB::OLE_F64] = "__ledf2";
+ Names[RTLIB::OGT_F32] = "__gtsf2";
+ Names[RTLIB::OGT_F64] = "__gtdf2";
+ Names[RTLIB::UO_F32] = "__unordsf2";
+ Names[RTLIB::UO_F64] = "__unorddf2";
+ Names[RTLIB::O_F32] = "__unordsf2";
+ Names[RTLIB::O_F64] = "__unorddf2";
+}
+
+/// InitCmpLibcallCCs - Set default comparison libcall CC.
+///
+static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
+ memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
+ CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
+ CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
+ CCs[RTLIB::UNE_F32] = ISD::SETNE;
+ CCs[RTLIB::UNE_F64] = ISD::SETNE;
+ CCs[RTLIB::OGE_F32] = ISD::SETGE;
+ CCs[RTLIB::OGE_F64] = ISD::SETGE;
+ CCs[RTLIB::OLT_F32] = ISD::SETLT;
+ CCs[RTLIB::OLT_F64] = ISD::SETLT;
+ CCs[RTLIB::OLE_F32] = ISD::SETLE;
+ CCs[RTLIB::OLE_F64] = ISD::SETLE;
+ CCs[RTLIB::OGT_F32] = ISD::SETGT;
+ CCs[RTLIB::OGT_F64] = ISD::SETGT;
+ CCs[RTLIB::UO_F32] = ISD::SETNE;
+ CCs[RTLIB::UO_F64] = ISD::SETNE;
+ CCs[RTLIB::O_F32] = ISD::SETEQ;
+ CCs[RTLIB::O_F64] = ISD::SETEQ;
+}
+
TargetLowering::TargetLowering(TargetMachine &tm)
: TM(tm), TD(TM.getTargetData()) {
assert(ISD::BUILTIN_OP_END <= 156 &&
"Fixed size array in TargetLowering is not large enough!");
// All operations default to being supported.
memset(OpActions, 0, sizeof(OpActions));
+ memset(LoadXActions, 0, sizeof(LoadXActions));
+ memset(&StoreXActions, 0, sizeof(StoreXActions));
+ // Initialize all indexed load / store to expand.
+ for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
+ for (unsigned IM = (unsigned)ISD::PRE_INC;
+ IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
+ setIndexedLoadAction(IM, (MVT::ValueType)VT, Expand);
+ setIndexedStoreAction(IM, (MVT::ValueType)VT, Expand);
+ }
+ }
IsLittleEndian = TD->isLittleEndian();
+ UsesGlobalOffsetTable = false;
ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD->getIntPtrType());
ShiftAmtHandling = Undefined;
memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
sizeof(TargetDAGCombineArray)/sizeof(TargetDAGCombineArray[0]));
maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
allowUnalignedMemoryAccesses = false;
- UseUnderscoreSetJmpLongJmp = false;
+ UseUnderscoreSetJmp = false;
+ UseUnderscoreLongJmp = false;
+ SelectIsExpensive = false;
IntDivIsCheap = false;
Pow2DivIsCheap = false;
StackPointerRegisterToSaveRestore = 0;
+ ExceptionPointerRegister = 0;
+ ExceptionSelectorRegister = 0;
SchedPreferenceInfo = SchedulingForLatency;
+ JumpBufSize = 0;
+ JumpBufAlignment = 0;
+
+ InitLibcallNames(LibcallRoutineNames);
+ InitCmpLibcallCCs(CmpLibcallCCs);
}
TargetLowering::~TargetLowering() {}
assert(VT < PromoteTo && "Must promote to a larger type!");
TransformToType[VT] = PromoteTo;
} else if (Action == TargetLowering::Expand) {
- assert((VT == MVT::Vector || MVT::isInteger(VT)) && VT > MVT::i8 &&
- "Cannot expand this type: target must support SOME integer reg!");
- // Expand to the next smaller integer type!
- TransformToType[VT] = (MVT::ValueType)(VT-1);
+ // f32 and f64 is each expanded to corresponding integer type of same size.
+ if (VT == MVT::f32)
+ TransformToType[VT] = MVT::i32;
+ else if (VT == MVT::f64)
+ TransformToType[VT] = MVT::i64;
+ else {
+ assert((VT == MVT::Vector || MVT::isInteger(VT)) && VT > MVT::i8 &&
+ "Cannot expand this type: target must support SOME integer reg!");
+ // Expand to the next smaller integer type!
+ TransformToType[VT] = (MVT::ValueType)(VT-1);
+ }
}
}
else
TransformToType[(MVT::ValueType)IntReg] = (MVT::ValueType)IntReg;
- // If the target does not have native support for F32, promote it to F64.
- if (!isTypeLegal(MVT::f32))
- SetValueTypeAction(MVT::f32, Promote, *this,
- TransformToType, ValueTypeActions);
- else
+ // If the target does not have native F64 support, expand it to I64. We will
+ // be generating soft float library calls. If the target does not have native
+ // support for F32, promote it to F64 if it is legal. Otherwise, expand it to
+ // I32.
+ if (isTypeLegal(MVT::f64))
+ TransformToType[MVT::f64] = MVT::f64;
+ else {
+ NumElementsForVT[MVT::f64] = NumElementsForVT[MVT::i64];
+ SetValueTypeAction(MVT::f64, Expand, *this, TransformToType,
+ ValueTypeActions);
+ }
+ if (isTypeLegal(MVT::f32))
TransformToType[MVT::f32] = MVT::f32;
+ else if (isTypeLegal(MVT::f64))
+ SetValueTypeAction(MVT::f32, Promote, *this, TransformToType,
+ ValueTypeActions);
+ else {
+ NumElementsForVT[MVT::f32] = NumElementsForVT[MVT::i32];
+ SetValueTypeAction(MVT::f32, Expand, *this, TransformToType,
+ ValueTypeActions);
+ }
// Set MVT::Vector to always be Expanded
SetValueTypeAction(MVT::Vector, Expand, *this, TransformToType,
if (isTypeLegal((MVT::ValueType)i))
TransformToType[i] = (MVT::ValueType)i;
}
-
- assert(isTypeLegal(MVT::f64) && "Target does not support FP?");
- TransformToType[MVT::f64] = MVT::f64;
}
const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
return NULL;
}
-/// getPackedTypeBreakdown - Packed types are broken down into some number of
-/// legal scalar types. For example, <8 x float> maps to 2 MVT::v2f32 values
+/// getVectorTypeBreakdown - Packed types are broken down into some number of
+/// legal first class types. For example, <8 x float> maps to 2 MVT::v4f32
/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
///
/// This method returns the number and type of the resultant breakdown.
///
-unsigned TargetLowering::getPackedTypeBreakdown(const PackedType *PTy,
+unsigned TargetLowering::getVectorTypeBreakdown(const VectorType *PTy,
MVT::ValueType &PTyElementVT,
MVT::ValueType &PTyLegalElementVT) const {
// Figure out the right, legal destination reg to copy into.
NumVectorRegs <<= 1;
}
- MVT::ValueType VT;
- if (NumElts == 1) {
+ MVT::ValueType VT = getVectorType(EltTy, NumElts);
+ if (!isTypeLegal(VT))
VT = EltTy;
- } else {
- VT = getVectorType(EltTy, NumElts);
- }
PTyElementVT = VT;
MVT::ValueType DestVT = getTypeToTransformTo(VT);
return NumVectorRegs;
}
- return DestVT;
+ return 1;
}
//===----------------------------------------------------------------------===//
return TLO.CombineTo(Op, Op.getOperand(0));
if ((DemandedMask & KnownZero2) == DemandedMask)
return TLO.CombineTo(Op, Op.getOperand(1));
+
+ // If all of the unknown bits are known to be zero on one side or the other
+ // (but not both) turn this into an *inclusive* or.
+ // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
+ if ((DemandedMask & ~KnownZero & ~KnownZero2) == 0)
+ return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(),
+ Op.getOperand(0),
+ Op.getOperand(1)));
// Output known-0 bits are known if clear or set in both the LHS & RHS.
KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
// Output known-1 are known to be set if set in only one of the LHS, RHS.
KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
- // If all of the unknown bits are known to be zero on one side or the other
- // (but not both) turn this into an *inclusive* or.
- // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
- if (uint64_t UnknownBits = DemandedMask & ~(KnownZeroOut|KnownOneOut))
- if ((UnknownBits & (KnownZero|KnownZero2)) == UnknownBits)
- return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(),
- Op.getOperand(0),
- Op.getOperand(1)));
// If all of the demanded bits on one side are known, and all of the set
// bits on that side are also known to be set on the other side, turn this
// into an AND, as we know the bits will be cleared.
break;
case ISD::SHL:
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
- if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask >> SA->getValue(),
+ unsigned ShAmt = SA->getValue();
+ SDOperand InOp = Op.getOperand(0);
+
+ // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
+ // single shift. We can do this if the bottom bits (which are shifted
+ // out) are never demanded.
+ if (InOp.getOpcode() == ISD::SRL &&
+ isa<ConstantSDNode>(InOp.getOperand(1))) {
+ if (ShAmt && (DemandedMask & ((1ULL << ShAmt)-1)) == 0) {
+ unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue();
+ unsigned Opc = ISD::SHL;
+ int Diff = ShAmt-C1;
+ if (Diff < 0) {
+ Diff = -Diff;
+ Opc = ISD::SRL;
+ }
+
+ SDOperand NewSA =
+ TLO.DAG.getConstant(ShAmt-C1, Op.getOperand(1).getValueType());
+ MVT::ValueType VT = Op.getValueType();
+ return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT,
+ InOp.getOperand(0), NewSA));
+ }
+ }
+
+ if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask >> ShAmt,
KnownZero, KnownOne, TLO, Depth+1))
return true;
KnownZero <<= SA->getValue();
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
MVT::ValueType VT = Op.getValueType();
unsigned ShAmt = SA->getValue();
-
- // Compute the new bits that are at the top now.
- uint64_t HighBits = (1ULL << ShAmt)-1;
- HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
uint64_t TypeMask = MVT::getIntVTBitMask(VT);
+ unsigned VTSize = MVT::getSizeInBits(VT);
+ SDOperand InOp = Op.getOperand(0);
- if (SimplifyDemandedBits(Op.getOperand(0),
- (DemandedMask << ShAmt) & TypeMask,
+ // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
+ // single shift. We can do this if the top bits (which are shifted out)
+ // are never demanded.
+ if (InOp.getOpcode() == ISD::SHL &&
+ isa<ConstantSDNode>(InOp.getOperand(1))) {
+ if (ShAmt && (DemandedMask & (~0ULL << (VTSize-ShAmt))) == 0) {
+ unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue();
+ unsigned Opc = ISD::SRL;
+ int Diff = ShAmt-C1;
+ if (Diff < 0) {
+ Diff = -Diff;
+ Opc = ISD::SHL;
+ }
+
+ SDOperand NewSA =
+ TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
+ return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT,
+ InOp.getOperand(0), NewSA));
+ }
+ }
+
+ // Compute the new bits that are at the top now.
+ if (SimplifyDemandedBits(InOp, (DemandedMask << ShAmt) & TypeMask,
KnownZero, KnownOne, TLO, Depth+1))
return true;
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
KnownOne &= TypeMask;
KnownZero >>= ShAmt;
KnownOne >>= ShAmt;
- KnownZero |= HighBits; // high bits known zero.
+
+ uint64_t HighBits = (1ULL << ShAmt)-1;
+ HighBits <<= VTSize - ShAmt;
+ KnownZero |= HighBits; // High bits known zero.
}
break;
case ISD::SRA:
unsigned ShAmt = SA->getValue();
// Compute the new bits that are at the top now.
- uint64_t HighBits = (1ULL << ShAmt)-1;
- HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
uint64_t TypeMask = MVT::getIntVTBitMask(VT);
uint64_t InDemandedMask = (DemandedMask << ShAmt) & TypeMask;
// If any of the demanded bits are produced by the sign extension, we also
// demand the input sign bit.
+ uint64_t HighBits = (1ULL << ShAmt)-1;
+ HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
if (HighBits & DemandedMask)
InDemandedMask |= MVT::getIntVTSignBit(VT);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
KnownZero &= TypeMask;
KnownOne &= TypeMask;
- KnownZero >>= SA->getValue();
- KnownOne >>= SA->getValue();
+ KnownZero >>= ShAmt;
+ KnownOne >>= ShAmt;
// Handle the sign bits.
uint64_t SignBit = MVT::getIntVTSignBit(VT);
- SignBit >>= SA->getValue(); // Adjust to where it is now in the mask.
+ SignBit >>= ShAmt; // Adjust to where it is now in the mask.
// If the input sign bit is known to be zero, or if none of the top bits
// are demanded, turn this into an unsigned shift right.
}
break;
case ISD::SIGN_EXTEND_INREG: {
- MVT::ValueType VT = Op.getValueType();
MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
// Sign extension. Compute the demanded bits in the result that are not
KnownOne = 0;
break;
}
- case ISD::ZEXTLOAD: {
- MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(3))->getVT();
- KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask;
+ case ISD::LOAD: {
+ if (ISD::isZEXTLoad(Op.Val)) {
+ LoadSDNode *LD = cast<LoadSDNode>(Op);
+ MVT::ValueType VT = LD->getLoadedVT();
+ KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask;
+ }
break;
}
case ISD::ZERO_EXTEND: {
// If none of the top bits are demanded, convert this into an any_extend.
if (NewBits == 0)
- return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(),
+ return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(),
Op.getOperand(0)));
// Since some of the sign extended bits are demanded, we know that the sign
case ISD::SHL:
// (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
- Mask >>= SA->getValue();
- ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
+ ComputeMaskedBits(Op.getOperand(0), Mask >> SA->getValue(),
+ KnownZero, KnownOne, Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
KnownZero <<= SA->getValue();
KnownOne <<= SA->getValue();
case ISD::SRL:
// (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
- uint64_t HighBits = (1ULL << SA->getValue())-1;
- HighBits <<= MVT::getSizeInBits(Op.getValueType())-SA->getValue();
- Mask <<= SA->getValue();
- ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
+ MVT::ValueType VT = Op.getValueType();
+ unsigned ShAmt = SA->getValue();
+
+ uint64_t TypeMask = MVT::getIntVTBitMask(VT);
+ ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt) & TypeMask,
+ KnownZero, KnownOne, Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
- KnownZero >>= SA->getValue();
- KnownOne >>= SA->getValue();
- KnownZero |= HighBits; // high bits known zero.
+ KnownZero &= TypeMask;
+ KnownOne &= TypeMask;
+ KnownZero >>= ShAmt;
+ KnownOne >>= ShAmt;
+
+ uint64_t HighBits = (1ULL << ShAmt)-1;
+ HighBits <<= MVT::getSizeInBits(VT)-ShAmt;
+ KnownZero |= HighBits; // High bits known zero.
}
return;
case ISD::SRA:
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
- uint64_t HighBits = (1ULL << SA->getValue())-1;
- HighBits <<= MVT::getSizeInBits(Op.getValueType())-SA->getValue();
- Mask <<= SA->getValue();
- ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
- assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?");
- KnownZero >>= SA->getValue();
- KnownOne >>= SA->getValue();
+ MVT::ValueType VT = Op.getValueType();
+ unsigned ShAmt = SA->getValue();
+
+ // Compute the new bits that are at the top now.
+ uint64_t TypeMask = MVT::getIntVTBitMask(VT);
+
+ uint64_t InDemandedMask = (Mask << ShAmt) & TypeMask;
+ // If any of the demanded bits are produced by the sign extension, we also
+ // demand the input sign bit.
+ uint64_t HighBits = (1ULL << ShAmt)-1;
+ HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
+ if (HighBits & Mask)
+ InDemandedMask |= MVT::getIntVTSignBit(VT);
+
+ ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne,
+ Depth+1);
+ assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
+ KnownZero &= TypeMask;
+ KnownOne &= TypeMask;
+ KnownZero >>= ShAmt;
+ KnownOne >>= ShAmt;
// Handle the sign bits.
- uint64_t SignBit = 1ULL << (MVT::getSizeInBits(Op.getValueType())-1);
- SignBit >>= SA->getValue(); // Adjust to where it is now in the mask.
+ uint64_t SignBit = MVT::getIntVTSignBit(VT);
+ SignBit >>= ShAmt; // Adjust to where it is now in the mask.
- if (KnownZero & SignBit) { // New bits are known zero.
- KnownZero |= HighBits;
- } else if (KnownOne & SignBit) { // New bits are known one.
- KnownOne |= HighBits;
+ if (KnownZero & SignBit) {
+ KnownZero |= HighBits; // New bits are known zero.
+ } else if (KnownOne & SignBit) {
+ KnownOne |= HighBits; // New bits are known one.
}
}
return;
case ISD::SIGN_EXTEND_INREG: {
- MVT::ValueType VT = Op.getValueType();
MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
// Sign extension. Compute the demanded bits in the result that are not
KnownOne = 0;
return;
}
- case ISD::ZEXTLOAD: {
- MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(3))->getVT();
- KnownZero |= ~MVT::getIntVTBitMask(VT) & Mask;
+ case ISD::LOAD: {
+ if (ISD::isZEXTLoad(Op.Val)) {
+ LoadSDNode *LD = cast<LoadSDNode>(Op);
+ MVT::ValueType VT = LD->getLoadedVT();
+ KnownZero |= ~MVT::getIntVTBitMask(VT) & Mask;
+ }
return;
}
case ISD::ZERO_EXTEND: {
KnownZero = ~((1ULL << (64-NLZ2))-1) & Mask; // Top bits known zero.
KnownOne = 0; // No one bits known.
} else {
- KnownOne = KnownOne = 0; // Otherwise, nothing known.
+ KnownZero = KnownOne = 0; // Otherwise, nothing known.
}
}
return;
case ISD::AssertZext:
Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
return VTBits-Tmp;
-
- case ISD::SEXTLOAD: // '17' bits known
- Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
- return VTBits-Tmp+1;
- case ISD::ZEXTLOAD: // '16' bits known
- Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
- return VTBits-Tmp;
case ISD::Constant: {
uint64_t Val = cast<ConstantSDNode>(Op)->getValue();
break;
}
+ // Handle LOADX separately here. EXTLOAD case will fallthrough.
+ if (Op.getOpcode() == ISD::LOAD) {
+ LoadSDNode *LD = cast<LoadSDNode>(Op);
+ unsigned ExtType = LD->getExtensionType();
+ switch (ExtType) {
+ default: break;
+ case ISD::SEXTLOAD: // '17' bits known
+ Tmp = MVT::getSizeInBits(LD->getLoadedVT());
+ return VTBits-Tmp+1;
+ case ISD::ZEXTLOAD: // '16' bits known
+ Tmp = MVT::getSizeInBits(LD->getLoadedVT());
+ return VTBits-Tmp;
+ }
+ }
+
// Allow the target to implement this method for its nodes.
if (Op.getOpcode() >= ISD::BUILTIN_OP_END ||
Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
}
+/// SimplifySetCC - Try to simplify a setcc built with the specified operands
+/// and cc. If it is unable to simplify it, return a null SDOperand.
+SDOperand
+TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
+ ISD::CondCode Cond, bool foldBooleans,
+ DAGCombinerInfo &DCI) const {
+ SelectionDAG &DAG = DCI.DAG;
+
+ // These setcc operations always fold.
+ switch (Cond) {
+ default: break;
+ case ISD::SETFALSE:
+ case ISD::SETFALSE2: return DAG.getConstant(0, VT);
+ case ISD::SETTRUE:
+ case ISD::SETTRUE2: return DAG.getConstant(1, VT);
+ }
+
+ if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
+ uint64_t C1 = N1C->getValue();
+ if (isa<ConstantSDNode>(N0.Val)) {
+ return DAG.FoldSetCC(VT, N0, N1, Cond);
+ } else {
+ // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
+ // equality comparison, then we're just comparing whether X itself is
+ // zero.
+ if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
+ N0.getOperand(0).getOpcode() == ISD::CTLZ &&
+ N0.getOperand(1).getOpcode() == ISD::Constant) {
+ unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
+ if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
+ ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) {
+ if ((C1 == 0) == (Cond == ISD::SETEQ)) {
+ // (srl (ctlz x), 5) == 0 -> X != 0
+ // (srl (ctlz x), 5) != 1 -> X != 0
+ Cond = ISD::SETNE;
+ } else {
+ // (srl (ctlz x), 5) != 0 -> X == 0
+ // (srl (ctlz x), 5) == 1 -> X == 0
+ Cond = ISD::SETEQ;
+ }
+ SDOperand Zero = DAG.getConstant(0, N0.getValueType());
+ return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0),
+ Zero, Cond);
+ }
+ }
+
+ // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
+ if (N0.getOpcode() == ISD::ZERO_EXTEND) {
+ unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
+
+ // If the comparison constant has bits in the upper part, the
+ // zero-extended value could never match.
+ if (C1 & (~0ULL << InSize)) {
+ unsigned VSize = MVT::getSizeInBits(N0.getValueType());
+ switch (Cond) {
+ case ISD::SETUGT:
+ case ISD::SETUGE:
+ case ISD::SETEQ: return DAG.getConstant(0, VT);
+ case ISD::SETULT:
+ case ISD::SETULE:
+ case ISD::SETNE: return DAG.getConstant(1, VT);
+ case ISD::SETGT:
+ case ISD::SETGE:
+ // True if the sign bit of C1 is set.
+ return DAG.getConstant((C1 & (1ULL << (VSize-1))) != 0, VT);
+ case ISD::SETLT:
+ case ISD::SETLE:
+ // True if the sign bit of C1 isn't set.
+ return DAG.getConstant((C1 & (1ULL << (VSize-1))) == 0, VT);
+ default:
+ break;
+ }
+ }
+
+ // Otherwise, we can perform the comparison with the low bits.
+ switch (Cond) {
+ case ISD::SETEQ:
+ case ISD::SETNE:
+ case ISD::SETUGT:
+ case ISD::SETUGE:
+ case ISD::SETULT:
+ case ISD::SETULE:
+ return DAG.getSetCC(VT, N0.getOperand(0),
+ DAG.getConstant(C1, N0.getOperand(0).getValueType()),
+ Cond);
+ default:
+ break; // todo, be more careful with signed comparisons
+ }
+ } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
+ (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
+ MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
+ unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
+ MVT::ValueType ExtDstTy = N0.getValueType();
+ unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
+
+ // If the extended part has any inconsistent bits, it cannot ever
+ // compare equal. In other words, they have to be all ones or all
+ // zeros.
+ uint64_t ExtBits =
+ (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
+ if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
+ return DAG.getConstant(Cond == ISD::SETNE, VT);
+
+ SDOperand ZextOp;
+ MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
+ if (Op0Ty == ExtSrcTy) {
+ ZextOp = N0.getOperand(0);
+ } else {
+ int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
+ ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
+ DAG.getConstant(Imm, Op0Ty));
+ }
+ if (!DCI.isCalledByLegalizer())
+ DCI.AddToWorklist(ZextOp.Val);
+ // Otherwise, make this a use of a zext.
+ return DAG.getSetCC(VT, ZextOp,
+ DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
+ ExtDstTy),
+ Cond);
+ } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
+ (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
+
+ // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
+ if (N0.getOpcode() == ISD::SETCC) {
+ bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1);
+ if (TrueWhenTrue)
+ return N0;
+
+ // Invert the condition.
+ ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
+ CC = ISD::getSetCCInverse(CC,
+ MVT::isInteger(N0.getOperand(0).getValueType()));
+ return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC);
+ }
+
+ if ((N0.getOpcode() == ISD::XOR ||
+ (N0.getOpcode() == ISD::AND &&
+ N0.getOperand(0).getOpcode() == ISD::XOR &&
+ N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
+ isa<ConstantSDNode>(N0.getOperand(1)) &&
+ cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
+ // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
+ // can only do this if the top bits are known zero.
+ if (MaskedValueIsZero(N0, MVT::getIntVTBitMask(N0.getValueType())-1)){
+ // Okay, get the un-inverted input value.
+ SDOperand Val;
+ if (N0.getOpcode() == ISD::XOR)
+ Val = N0.getOperand(0);
+ else {
+ assert(N0.getOpcode() == ISD::AND &&
+ N0.getOperand(0).getOpcode() == ISD::XOR);
+ // ((X^1)&1)^1 -> X & 1
+ Val = DAG.getNode(ISD::AND, N0.getValueType(),
+ N0.getOperand(0).getOperand(0),
+ N0.getOperand(1));
+ }
+ return DAG.getSetCC(VT, Val, N1,
+ Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
+ }
+ }
+ }
+
+ uint64_t MinVal, MaxVal;
+ unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
+ if (ISD::isSignedIntSetCC(Cond)) {
+ MinVal = 1ULL << (OperandBitSize-1);
+ if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
+ MaxVal = ~0ULL >> (65-OperandBitSize);
+ else
+ MaxVal = 0;
+ } else {
+ MinVal = 0;
+ MaxVal = ~0ULL >> (64-OperandBitSize);
+ }
+
+ // Canonicalize GE/LE comparisons to use GT/LT comparisons.
+ if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
+ if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
+ --C1; // X >= C0 --> X > (C0-1)
+ return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
+ (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
+ }
+
+ if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
+ if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
+ ++C1; // X <= C0 --> X < (C0+1)
+ return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
+ (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
+ }
+
+ if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
+ return DAG.getConstant(0, VT); // X < MIN --> false
+ if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
+ return DAG.getConstant(1, VT); // X >= MIN --> true
+ if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
+ return DAG.getConstant(0, VT); // X > MAX --> false
+ if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
+ return DAG.getConstant(1, VT); // X <= MAX --> true
+
+ // Canonicalize setgt X, Min --> setne X, Min
+ if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
+ return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
+ // Canonicalize setlt X, Max --> setne X, Max
+ if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
+ return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
+
+ // If we have setult X, 1, turn it into seteq X, 0
+ if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
+ return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
+ ISD::SETEQ);
+ // If we have setugt X, Max-1, turn it into seteq X, Max
+ else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
+ return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
+ ISD::SETEQ);
+
+ // If we have "setcc X, C0", check to see if we can shrink the immediate
+ // by changing cc.
+
+ // SETUGT X, SINTMAX -> SETLT X, 0
+ if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
+ C1 == (~0ULL >> (65-OperandBitSize)))
+ return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
+ ISD::SETLT);
+
+ // FIXME: Implement the rest of these.
+
+ // Fold bit comparisons when we can.
+ if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
+ VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
+ if (ConstantSDNode *AndRHS =
+ dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
+ if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
+ // Perform the xform if the AND RHS is a single bit.
+ if (isPowerOf2_64(AndRHS->getValue())) {
+ return DAG.getNode(ISD::SRL, VT, N0,
+ DAG.getConstant(Log2_64(AndRHS->getValue()),
+ getShiftAmountTy()));
+ }
+ } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
+ // (X & 8) == 8 --> (X & 8) >> 3
+ // Perform the xform if C1 is a single bit.
+ if (isPowerOf2_64(C1)) {
+ return DAG.getNode(ISD::SRL, VT, N0,
+ DAG.getConstant(Log2_64(C1), getShiftAmountTy()));
+ }
+ }
+ }
+ }
+ } else if (isa<ConstantSDNode>(N0.Val)) {
+ // Ensure that the constant occurs on the RHS.
+ return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
+ }
+
+ if (isa<ConstantFPSDNode>(N0.Val)) {
+ // Constant fold or commute setcc.
+ SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond);
+ if (O.Val) return O;
+ }
+
+ if (N0 == N1) {
+ // We can always fold X == X for integer setcc's.
+ if (MVT::isInteger(N0.getValueType()))
+ return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
+ unsigned UOF = ISD::getUnorderedFlavor(Cond);
+ if (UOF == 2) // FP operators that are undefined on NaNs.
+ return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
+ if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
+ return DAG.getConstant(UOF, VT);
+ // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
+ // if it is not already.
+ ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
+ if (NewCond != Cond)
+ return DAG.getSetCC(VT, N0, N1, NewCond);
+ }
+
+ if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
+ MVT::isInteger(N0.getValueType())) {
+ if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
+ N0.getOpcode() == ISD::XOR) {
+ // Simplify (X+Y) == (X+Z) --> Y == Z
+ if (N0.getOpcode() == N1.getOpcode()) {
+ if (N0.getOperand(0) == N1.getOperand(0))
+ return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
+ if (N0.getOperand(1) == N1.getOperand(1))
+ return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
+ if (DAG.isCommutativeBinOp(N0.getOpcode())) {
+ // If X op Y == Y op X, try other combinations.
+ if (N0.getOperand(0) == N1.getOperand(1))
+ return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
+ if (N0.getOperand(1) == N1.getOperand(0))
+ return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
+ }
+ }
+
+ if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
+ if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
+ // Turn (X+C1) == C2 --> X == C2-C1
+ if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
+ return DAG.getSetCC(VT, N0.getOperand(0),
+ DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
+ N0.getValueType()), Cond);
+ }
+
+ // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
+ if (N0.getOpcode() == ISD::XOR)
+ // If we know that all of the inverted bits are zero, don't bother
+ // performing the inversion.
+ if (MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
+ return DAG.getSetCC(VT, N0.getOperand(0),
+ DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
+ N0.getValueType()), Cond);
+ }
+
+ // Turn (C1-X) == C2 --> X == C1-C2
+ if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
+ if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
+ return DAG.getSetCC(VT, N0.getOperand(1),
+ DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
+ N0.getValueType()), Cond);
+ }
+ }
+ }
+
+ // Simplify (X+Z) == X --> Z == 0
+ if (N0.getOperand(0) == N1)
+ return DAG.getSetCC(VT, N0.getOperand(1),
+ DAG.getConstant(0, N0.getValueType()), Cond);
+ if (N0.getOperand(1) == N1) {
+ if (DAG.isCommutativeBinOp(N0.getOpcode()))
+ return DAG.getSetCC(VT, N0.getOperand(0),
+ DAG.getConstant(0, N0.getValueType()), Cond);
+ else {
+ assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
+ // (Z-X) == X --> Z == X<<1
+ SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
+ N1,
+ DAG.getConstant(1, getShiftAmountTy()));
+ if (!DCI.isCalledByLegalizer())
+ DCI.AddToWorklist(SH.Val);
+ return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
+ }
+ }
+ }
+
+ if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
+ N1.getOpcode() == ISD::XOR) {
+ // Simplify X == (X+Z) --> Z == 0
+ if (N1.getOperand(0) == N0) {
+ return DAG.getSetCC(VT, N1.getOperand(1),
+ DAG.getConstant(0, N1.getValueType()), Cond);
+ } else if (N1.getOperand(1) == N0) {
+ if (DAG.isCommutativeBinOp(N1.getOpcode())) {
+ return DAG.getSetCC(VT, N1.getOperand(0),
+ DAG.getConstant(0, N1.getValueType()), Cond);
+ } else {
+ assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
+ // X == (Z-X) --> X<<1 == Z
+ SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
+ DAG.getConstant(1, getShiftAmountTy()));
+ if (!DCI.isCalledByLegalizer())
+ DCI.AddToWorklist(SH.Val);
+ return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
+ }
+ }
+ }
+ }
+
+ // Fold away ALL boolean setcc's.
+ SDOperand Temp;
+ if (N0.getValueType() == MVT::i1 && foldBooleans) {
+ switch (Cond) {
+ default: assert(0 && "Unknown integer setcc!");
+ case ISD::SETEQ: // X == Y -> (X^Y)^1
+ Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
+ N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
+ if (!DCI.isCalledByLegalizer())
+ DCI.AddToWorklist(Temp.Val);
+ break;
+ case ISD::SETNE: // X != Y --> (X^Y)
+ N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
+ break;
+ case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
+ case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
+ Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
+ N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
+ if (!DCI.isCalledByLegalizer())
+ DCI.AddToWorklist(Temp.Val);
+ break;
+ case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
+ case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
+ Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
+ N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
+ if (!DCI.isCalledByLegalizer())
+ DCI.AddToWorklist(Temp.Val);
+ break;
+ case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
+ case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
+ Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
+ N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
+ if (!DCI.isCalledByLegalizer())
+ DCI.AddToWorklist(Temp.Val);
+ break;
+ case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
+ case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
+ Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
+ N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
+ break;
+ }
+ if (VT != MVT::i1) {
+ if (!DCI.isCalledByLegalizer())
+ DCI.AddToWorklist(N0.Val);
+ // FIXME: If running after legalize, we probably can't do this.
+ N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
+ }
+ return N0;
+ }
+
+ // Could not fold it.
+ return SDOperand();
+}
+
SDOperand TargetLowering::
PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
// Default implementation: no optimization.
//===----------------------------------------------------------------------===//
TargetLowering::ConstraintType
-TargetLowering::getConstraintType(char ConstraintLetter) const {
+TargetLowering::getConstraintType(const std::string &Constraint) const {
// FIXME: lots more standard ones to handle.
- switch (ConstraintLetter) {
- default: return C_Unknown;
- case 'r': return C_RegisterClass;
- case 'm': // memory
- case 'o': // offsetable
- case 'V': // not offsetable
- return C_Memory;
- case 'i': // Simple Integer or Relocatable Constant
- case 'n': // Simple Integer
- case 's': // Relocatable Constant
- case 'I': // Target registers.
- case 'J':
- case 'K':
- case 'L':
- case 'M':
- case 'N':
- case 'O':
- case 'P':
- return C_Other;
+ if (Constraint.size() == 1) {
+ switch (Constraint[0]) {
+ default: break;
+ case 'r': return C_RegisterClass;
+ case 'm': // memory
+ case 'o': // offsetable
+ case 'V': // not offsetable
+ return C_Memory;
+ case 'i': // Simple Integer or Relocatable Constant
+ case 'n': // Simple Integer
+ case 's': // Relocatable Constant
+ case 'X': // Allow ANY value.
+ case 'I': // Target registers.
+ case 'J':
+ case 'K':
+ case 'L':
+ case 'M':
+ case 'N':
+ case 'O':
+ case 'P':
+ return C_Other;
+ }
}
+
+ if (Constraint.size() > 1 && Constraint[0] == '{' &&
+ Constraint[Constraint.size()-1] == '}')
+ return C_Register;
+ return C_Unknown;
}
-bool TargetLowering::isOperandValidForConstraint(SDOperand Op,
- char ConstraintLetter) {
+/// isOperandValidForConstraint - Return the specified operand (possibly
+/// modified) if the specified SDOperand is valid for the specified target
+/// constraint letter, otherwise return null.
+SDOperand TargetLowering::isOperandValidForConstraint(SDOperand Op,
+ char ConstraintLetter,
+ SelectionDAG &DAG) {
switch (ConstraintLetter) {
- default: return false;
+ default: break;
case 'i': // Simple Integer or Relocatable Constant
case 'n': // Simple Integer
case 's': // Relocatable Constant
- return true; // FIXME: not right.
+ case 'X': { // Allows any operand.
+ // These operands are interested in values of the form (GV+C), where C may
+ // be folded in as an offset of GV, or it may be explicitly added. Also, it
+ // is possible and fine if either GV or C are missing.
+ ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
+ GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
+
+ // If we have "(add GV, C)", pull out GV/C
+ if (Op.getOpcode() == ISD::ADD) {
+ C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
+ GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
+ if (C == 0 || GA == 0) {
+ C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
+ GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
+ }
+ if (C == 0 || GA == 0)
+ C = 0, GA = 0;
+ }
+
+ // If we find a valid operand, map to the TargetXXX version so that the
+ // value itself doesn't get selected.
+ if (GA) { // Either &GV or &GV+C
+ if (ConstraintLetter != 'n') {
+ int64_t Offs = GA->getOffset();
+ if (C) Offs += C->getValue();
+ return DAG.getTargetGlobalAddress(GA->getGlobal(), Op.getValueType(),
+ Offs);
+ }
+ }
+ if (C) { // just C, no GV.
+ // Simple constants are not allowed for 's'.
+ if (ConstraintLetter != 's')
+ return DAG.getTargetConstant(C->getValue(), Op.getValueType());
+ }
+ break;
}
+ }
+ return SDOperand(0,0);
}
-
std::vector<unsigned> TargetLowering::
getRegClassForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const {
// Loop Strength Reduction hooks
//===----------------------------------------------------------------------===//
-/// isLegalAddressImmediate - Return true if the integer value or
-/// GlobalValue can be used as the offset of the target addressing mode.
-bool TargetLowering::isLegalAddressImmediate(int64_t V) const {
- return false;
-}
-bool TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {
- return false;
-}
+/// isLegalAddressingMode - Return true if the addressing mode represented
+/// by AM is legal for this target, for a load/store of the specified type.
+bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
+ const Type *Ty) const {
+ // The default implementation of this implements a conservative RISCy, r+r and
+ // r+i addr mode.
+ // Allows a sign-extended 16-bit immediate field.
+ if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
+ return false;
+
+ // No global is ever allowed as a base.
+ if (AM.BaseGV)
+ return false;
+
+ // Only support r+r,
+ switch (AM.Scale) {
+ case 0: // "r+i" or just "i", depending on HasBaseReg.
+ break;
+ case 1:
+ if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
+ return false;
+ // Otherwise we have r+r or r+i.
+ break;
+ case 2:
+ if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
+ return false;
+ // Allow 2*r as r+r.
+ break;
+ }
+
+ return true;
+}
// Magic for divide replacement
r2 = 2*r2 + 1; // update r2
}
delta = d - 1 - r2;
- } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
+ } while (p < 128 && (q1 < delta || (q1 == delta && r1 == 0)));
magu.m = q2 + 1; // resulting magic number
magu.s = p - 64; // resulting shift
return magu;
/// multiplying by a magic number. See:
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
- std::list<SDNode*>* Created) const {
+ std::vector<SDNode*>* Created) const {
MVT::ValueType VT = N->getValueType(0);
// Check to see if we can do this.
/// multiplying by a magic number. See:
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
- std::list<SDNode*>* Created) const {
+ std::vector<SDNode*>* Created) const {
MVT::ValueType VT = N->getValueType(0);
// Check to see if we can do this.
projects / oota-llvm.git / blobdiff