#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/DerivedTypes.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/Support/MathExtras.h"
// Set MVT::Vector to always be Expanded
SetValueTypeAction(MVT::Vector, Expand, *this, TransformToType,
ValueTypeActions);
+
+ // Loop over all of the legal vector value types, specifying an identity type
+ // transformation.
+ for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
+ i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
+ if (isTypeLegal((MVT::ValueType)i))
+ TransformToType[i] = (MVT::ValueType)i;
+ }
assert(isTypeLegal(MVT::f64) && "Target does not support FP?");
TransformToType[MVT::f64] = MVT::f64;
return NULL;
}
+/// getPackedTypeBreakdown - Packed types are broken down into some number of
+/// legal scalar types. For example, <8 x float> maps to 2 MVT::v2f32 values
+/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
+///
+/// This method returns the number and type of the resultant breakdown.
+///
+unsigned TargetLowering::getPackedTypeBreakdown(const PackedType *PTy,
+ MVT::ValueType &PTyElementVT,
+ MVT::ValueType &PTyLegalElementVT) const {
+ // Figure out the right, legal destination reg to copy into.
+ unsigned NumElts = PTy->getNumElements();
+ MVT::ValueType EltTy = getValueType(PTy->getElementType());
+
+ unsigned NumVectorRegs = 1;
+
+ // Divide the input until we get to a supported size. This will always
+ // end with a scalar if the target doesn't support vectors.
+ while (NumElts > 1 && !isTypeLegal(getVectorType(EltTy, NumElts))) {
+ NumElts >>= 1;
+ NumVectorRegs <<= 1;
+ }
+
+ MVT::ValueType VT;
+ if (NumElts == 1) {
+ VT = EltTy;
+ } else {
+ VT = getVectorType(EltTy, NumElts);
+ }
+ PTyElementVT = VT;
+
+ MVT::ValueType DestVT = getTypeToTransformTo(VT);
+ PTyLegalElementVT = DestVT;
+ if (DestVT < VT) {
+ // Value is expanded, e.g. i64 -> i16.
+ return NumVectorRegs*(MVT::getSizeInBits(VT)/MVT::getSizeInBits(DestVT));
+ } else {
+ // Otherwise, promotion or legal types use the same number of registers as
+ // the vector decimated to the appropriate level.
+ return NumVectorRegs;
+ }
+
+ return DestVT;
+}
+
//===----------------------------------------------------------------------===//
// Optimization Methods
//===----------------------------------------------------------------------===//
break;
}
case ISD::ADD:
- if (ConstantSDNode *AA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
- if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero,
- KnownOne, TLO, Depth+1))
- return true;
- // Compute the KnownOne/KnownZero masks for the constant, so we can set
- // KnownZero appropriately if we're adding a constant that has all low
- // bits cleared.
- ComputeMaskedBits(Op.getOperand(1),
- MVT::getIntVTBitMask(Op.getValueType()),
- KnownZero2, KnownOne2, Depth+1);
-
- uint64_t KnownZeroOut = std::min(CountTrailingZeros_64(~KnownZero),
- CountTrailingZeros_64(~KnownZero2));
- KnownZero = (1ULL << KnownZeroOut) - 1;
- KnownOne = 0;
- }
- break;
case ISD::SUB:
- // Just use ComputeMaskedBits to compute output bits, there are no
- // simplifications that can be done here, and sub always demands all input
- // bits.
+ case ISD::INTRINSIC_WO_CHAIN:
+ case ISD::INTRINSIC_W_CHAIN:
+ case ISD::INTRINSIC_VOID:
+ // Just use ComputeMaskedBits to compute output bits.
ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
break;
}
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
// Output known-0 bits are known if clear or set in both the low clear bits
- // common to both LHS & RHS;
+ // common to both LHS & RHS. For example, 8+(X<<3) is known to have the
+ // low 3 bits clear.
uint64_t KnownZeroOut = std::min(CountTrailingZeros_64(~KnownZero),
CountTrailingZeros_64(~KnownZero2));
}
default:
// Allow the target to implement this method for its nodes.
- if (Op.getOpcode() >= ISD::BUILTIN_OP_END)
+ if (Op.getOpcode() >= ISD::BUILTIN_OP_END) {
+ case ISD::INTRINSIC_WO_CHAIN:
+ case ISD::INTRINSIC_W_CHAIN:
+ case ISD::INTRINSIC_VOID:
computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne);
+ }
return;
}
}
uint64_t &KnownZero,
uint64_t &KnownOne,
unsigned Depth) const {
- assert(Op.getOpcode() >= ISD::BUILTIN_OP_END &&
+ assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
+ Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
+ Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
+ Op.getOpcode() == ISD::INTRINSIC_VOID) &&
"Should use MaskedValueIsZero if you don't know whether Op"
" is a target node!");
KnownZero = 0;
return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
}
+
+//===----------------------------------------------------------------------===//
+// Loop Strength Reduction hooks
+//===----------------------------------------------------------------------===//
+
+/// isLegalAddressImmediate - Return true if the integer value or
+/// GlobalValue can be used as the offset of the target addressing mode.
+bool TargetLowering::isLegalAddressImmediate(int64_t V) const {
+ return false;
+}
+bool TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {
+ return false;
+}
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