// Figure out the right, legal destination reg to copy into.
unsigned NumElts = PTy->getNumElements();
MVT::ValueType EltTy = getValueType(PTy->getElementType());
- PTyElementVT = EltTy;
unsigned NumVectorRegs = 1;
}
MVT::ValueType VT;
- if (NumElts == 1)
+ if (NumElts == 1) {
VT = EltTy;
- else
- VT = getVectorType(EltTy, NumElts);
+ } else {
+ VT = getVectorType(EltTy, NumElts);
+ }
+ PTyElementVT = VT;
MVT::ValueType DestVT = getTypeToTransformTo(VT);
PTyLegalElementVT = DestVT;
}
case ISD::ADD:
case ISD::SUB:
- // Just use ComputeMaskedBits to compute output bits, there are no
- // simplifications that can be done here, and sub always demands all input
- // bits.
+ case ISD::INTRINSIC_WO_CHAIN:
+ case ISD::INTRINSIC_W_CHAIN:
+ case ISD::INTRINSIC_VOID:
+ // Just use ComputeMaskedBits to compute output bits.
ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
break;
}
}
default:
// Allow the target to implement this method for its nodes.
- if (Op.getOpcode() >= ISD::BUILTIN_OP_END)
+ if (Op.getOpcode() >= ISD::BUILTIN_OP_END) {
+ case ISD::INTRINSIC_WO_CHAIN:
+ case ISD::INTRINSIC_W_CHAIN:
+ case ISD::INTRINSIC_VOID:
computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne);
+ }
return;
}
}
uint64_t &KnownZero,
uint64_t &KnownOne,
unsigned Depth) const {
- assert(Op.getOpcode() >= ISD::BUILTIN_OP_END &&
+ assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
+ Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
+ Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
+ Op.getOpcode() == ISD::INTRINSIC_VOID) &&
"Should use MaskedValueIsZero if you don't know whether Op"
" is a target node!");
KnownZero = 0;