const PassInfo *const llvm::SimpleRegisterCoalescingID = &X;
void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.addRequired<LiveIntervals>();
AU.addPreserved<LiveIntervals>();
+ AU.addRequired<MachineLoopInfo>();
AU.addPreserved<MachineLoopInfo>();
AU.addPreservedID(MachineDominatorsID);
AU.addPreservedID(PHIEliminationID);
AU.addPreservedID(TwoAddressInstructionPassID);
- AU.addRequired<LiveIntervals>();
- AU.addRequired<MachineLoopInfo>();
MachineFunctionPass::getAnalysisUsage(AU);
}
DOUT << " and "; DstInt.print(DOUT, tri_);
DOUT << ": ";
- // If one interval is earlyclobber and the other is overlaps-earlyclobber,
- // we cannot coalesce them.
- if ((SrcInt.isEarlyClobber && DstInt.overlapsEarlyClobber) ||
- (DstInt.isEarlyClobber && SrcInt.overlapsEarlyClobber)) {
- DOUT << "\t\tCannot join due to earlyclobber.";
- return false;
- }
-
// Check if it is necessary to propagate "isDead" property.
if (!isExtSubReg && !isInsSubReg) {
MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
if (TargetRegisterInfo::isVirtualRegister(DstReg))
RemoveUnnecessaryKills(DstReg, *ResDstInt);
- // Merge the earlyclobber bits.
- ResDstInt->isEarlyClobber |= ResSrcInt->isEarlyClobber;
- ResDstInt->overlapsEarlyClobber |= ResSrcInt->overlapsEarlyClobber;
-
if (isInsSubReg)
// Avoid:
// r1024 = op
LI.weight = HUGE_VALF;
else {
bool isLoad = false;
- if (li_->isReMaterializable(LI, isLoad)) {
+ SmallVector<LiveInterval*, 4> SpillIs;
+ if (li_->isReMaterializable(LI, SpillIs, isLoad)) {
// If all of the definitions of the interval are re-materializable,
// it is a preferred candidate for spilling. If non of the defs are
// loads, then it's potentially very cheap to re-materialize.