//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "regcoalescing"
-#include "llvm/CodeGen/SimpleRegisterCoalescing.h"
-#include "llvm/CodeGen/LiveIntervalAnalysis.h"
+#include "SimpleRegisterCoalescing.h"
#include "VirtRegMap.h"
+#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/Value.h"
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/CodeGen/LiveVariables.h"
const PassInfo *llvm::SimpleRegisterCoalescingID = X.getPassInfo();
void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
- //AU.addPreserved<LiveVariables>();
AU.addPreserved<LiveIntervals>();
AU.addPreservedID(PHIEliminationID);
AU.addPreservedID(TwoAddressInstructionPassID);
return true;
}
+/// AddSubRegIdxPairs - Recursively mark all the registers represented by the
+/// specified register as sub-registers. The recursion level is expected to be
+/// shallow.
+void SimpleRegisterCoalescing::AddSubRegIdxPairs(unsigned Reg, unsigned SubIdx) {
+ std::vector<unsigned> &JoinedRegs = r2rRevMap_[Reg];
+ for (unsigned i = 0, e = JoinedRegs.size(); i != e; ++i) {
+ SubRegIdxes.push_back(std::make_pair(JoinedRegs[i], SubIdx));
+ AddSubRegIdxPairs(JoinedRegs[i], SubIdx);
+ }
+}
+
/// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
/// which are the src/dst of the copy instruction CopyMI. This returns true
-/// if the copy was successfully coalesced away, or if it is never possible
-/// to coalesce this copy, due to register constraints. It returns
-/// false if it is not currently possible to coalesce this interval, but
-/// it may be possible if other things get coalesced.
+/// if the copy was successfully coalesced away. If it is not currently
+/// possible to coalesce this interval, but it may be possible if other
+/// things get coalesced, then it returns true by reference in 'Again'.
bool SimpleRegisterCoalescing::JoinCopy(MachineInstr *CopyMI,
- unsigned SrcReg, unsigned DstReg, bool PhysOnly) {
+ unsigned SrcReg, unsigned DstReg,
+ bool &Again) {
DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
// Get representative registers.
unsigned repSrcReg = rep(SrcReg);
unsigned repDstReg = rep(DstReg);
+ Again = false;
+
// If they are already joined we continue.
if (repSrcReg == repDstReg) {
DOUT << "\tCopy already coalesced.\n";
- return true; // Not coalescable.
+ return false; // Not coalescable.
}
bool SrcIsPhys = MRegisterInfo::isPhysicalRegister(repSrcReg);
bool DstIsPhys = MRegisterInfo::isPhysicalRegister(repDstReg);
- if (PhysOnly && !SrcIsPhys && !DstIsPhys)
- // Only joining physical registers with virtual registers in this round.
- return true;
// If they are both physical registers, we cannot join them.
if (SrcIsPhys && DstIsPhys) {
DOUT << "\tCan not coalesce physregs.\n";
- return true; // Not coalescable.
+ return false; // Not coalescable.
}
// We only join virtual registers with allocatable physical registers.
if (SrcIsPhys && !allocatableRegs_[repSrcReg]) {
DOUT << "\tSrc reg is unallocatable physreg.\n";
- return true; // Not coalescable.
+ return false; // Not coalescable.
}
if (DstIsPhys && !allocatableRegs_[repDstReg]) {
DOUT << "\tDst reg is unallocatable physreg.\n";
- return true; // Not coalescable.
+ return false; // Not coalescable.
}
bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG;
// If this is a extract_subreg where dst is a physical register, e.g.
// cl = EXTRACT_SUBREG reg1024, 1
// then create and update the actual physical register allocated to RHS.
- const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(SrcReg);
+ const TargetRegisterClass *RC=mf_->getSSARegMap()->getRegClass(repSrcReg);
for (const unsigned *SRs = mri_->getSuperRegisters(repDstReg);
unsigned SR = *SRs; ++SRs) {
if (repDstReg == mri_->getSubReg(SR, SubIdx) &&
RHS.overlaps(li_->getInterval(RealDstReg))) {
DOUT << "Interfere with register ";
DEBUG(li_->getInterval(RealDstReg).print(DOUT, mri_));
- return true; // Not coalescable
+ return false; // Not coalescable
}
for (const unsigned* SR = mri_->getSubRegisters(RealDstReg); *SR; ++SR)
if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
DOUT << "Interfere with sub-register ";
DEBUG(li_->getInterval(*SR).print(DOUT, mri_));
- return true; // Not coalescable
+ return false; // Not coalescable
}
- } else if (li_->getInterval(repDstReg).getSize() >
- li_->getInterval(repSrcReg).getSize()) {
+ } else {
+ unsigned SrcSize= li_->getInterval(repSrcReg).getSize() / InstrSlots::NUM;
+ unsigned DstSize= li_->getInterval(repDstReg).getSize() / InstrSlots::NUM;
+ const TargetRegisterClass *RC=mf_->getSSARegMap()->getRegClass(repDstReg);
+ unsigned Threshold = allocatableRCRegs_[RC].count();
// Be conservative. If both sides are virtual registers, do not coalesce
- // if the sub-register live interval is longer.
- return false;
+ // if this will cause a high use density interval to target a smaller set
+ // of registers.
+ if (DstSize > Threshold || SrcSize > Threshold) {
+ LiveVariables::VarInfo &svi = lv_->getVarInfo(repSrcReg);
+ LiveVariables::VarInfo &dvi = lv_->getVarInfo(repDstReg);
+ if ((float)dvi.NumUses / DstSize < (float)svi.NumUses / SrcSize) {
+ Again = true; // May be possible to coalesce later.
+ return false;
+ }
+ }
}
} else if (differingRegisterClasses(repSrcReg, repDstReg)) {
// If they are not of the same register class, we cannot join them.
// a physical register that's compatible with the other side. e.g.
// r1024 = MOV32to32_ r1025
// but later r1024 is assigned EAX then r1025 may be coalesced with EAX.
+ Again = true; // May be possible to coalesce later.
return false;
}
JoinVInt.preference = JoinPReg;
++numAborts;
DOUT << "\tMay tie down a physical register, abort!\n";
+ Again = true; // May be possible to coalesce later.
return false;
}
}
// Otherwise, we are unable to join the intervals.
DOUT << "Interference!\n";
+ Again = true; // May be possible to coalesce later.
return false;
}
std::swap(repSrcReg, repDstReg);
std::swap(ResSrcInt, ResDstInt);
}
- SubRegIdxes.push_back(std::make_pair(repSrcReg,
- CopyMI->getOperand(2).getImm()));
+ unsigned SubIdx = CopyMI->getOperand(2).getImm();
+ SubRegIdxes.push_back(std::make_pair(repSrcReg, SubIdx));
+ AddSubRegIdxPairs(repSrcReg, SubIdx);
}
DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, mri_);
// being merged.
li_->removeInterval(repSrcReg);
r2rMap_[repSrcReg] = repDstReg;
+ r2rRevMap_[repDstReg].push_back(repSrcReg);
// Finally, delete the copy instruction.
li_->RemoveMachineInstrFromMaps(CopyMI);
i != e; ++i) {
VNInfo *VNI = *i;
unsigned ValSrcReg = VNI->reg;
- if (ValSrcReg == 0) // Src not defined by a copy?
+ if (VNI->def == ~1U ||ValSrcReg == 0) // Src not defined by a copy?
continue;
// DstReg is known to be a register in the LHS interval. If the src is
i != e; ++i) {
VNInfo *VNI = *i;
unsigned ValSrcReg = VNI->reg;
- if (ValSrcReg == 0) // Src not defined by a copy?
+ if (VNI->def == ~1U || ValSrcReg == 0) // Src not defined by a copy?
continue;
// DstReg is known to be a register in the RHS interval. If the src is
}
void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
- std::vector<CopyRec> *TryAgain, bool PhysOnly) {
+ std::vector<CopyRec> &TryAgain) {
DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
+ std::vector<CopyRec> VirtCopies;
+ std::vector<CopyRec> PhysCopies;
for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
MII != E;) {
MachineInstr *Inst = MII++;
SrcReg = Inst->getOperand(1).getReg();
} else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg))
continue;
-
- bool Done = JoinCopy(Inst, SrcReg, DstReg, PhysOnly);
- if (TryAgain && !Done)
- TryAgain->push_back(getCopyRec(Inst, SrcReg, DstReg));
+
+ unsigned repSrcReg = rep(SrcReg);
+ unsigned repDstReg = rep(DstReg);
+ bool SrcIsPhys = MRegisterInfo::isPhysicalRegister(repSrcReg);
+ bool DstIsPhys = MRegisterInfo::isPhysicalRegister(repDstReg);
+ if (SrcIsPhys || DstIsPhys)
+ PhysCopies.push_back(getCopyRec(Inst, SrcReg, DstReg));
+ else
+ VirtCopies.push_back(getCopyRec(Inst, SrcReg, DstReg));
+ }
+
+ // Try coalescing physical register + virtual register first.
+ for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
+ CopyRec &TheCopy = PhysCopies[i];
+ bool Again = false;
+ if (!JoinCopy(TheCopy.MI, TheCopy.SrcReg, TheCopy.DstReg, Again))
+ if (Again)
+ TryAgain.push_back(TheCopy);
+ }
+ for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
+ CopyRec &TheCopy = VirtCopies[i];
+ bool Again = false;
+ if (!JoinCopy(TheCopy.MI, TheCopy.SrcReg, TheCopy.DstReg, Again))
+ if (Again)
+ TryAgain.push_back(TheCopy);
}
}
// If there are no loops in the function, join intervals in function order.
for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
I != E; ++I)
- CopyCoalesceInMBB(I, &TryAgainList);
+ CopyCoalesceInMBB(I, TryAgainList);
} else {
// Otherwise, join intervals in inner loops before other intervals.
// Unfortunately we can't just iterate over loop hierarchy here because
// Finally, join intervals in loop nest order.
for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
- CopyCoalesceInMBB(MBBs[i].second, NULL, true);
- for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
- CopyCoalesceInMBB(MBBs[i].second, &TryAgainList, false);
+ CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
}
// Joining intervals can allow other intervals to be joined. Iteratively join
for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
CopyRec &TheCopy = TryAgainList[i];
- if (TheCopy.MI &&
- JoinCopy(TheCopy.MI, TheCopy.SrcReg, TheCopy.DstReg)) {
- TheCopy.MI = 0; // Mark this one as done.
- ProgressMade = true;
+ if (TheCopy.MI) {
+ bool Again = false;
+ bool Success = JoinCopy(TheCopy.MI,TheCopy.SrcReg,TheCopy.DstReg,Again);
+ if (Success || !Again) {
+ TheCopy.MI = 0; // Mark this one as done.
+ ProgressMade = true;
+ }
}
}
}
}
DOUT << "*** Register mapping ***\n";
- for (int i = 0, e = r2rMap_.size(); i != e; ++i)
+ for (unsigned i = 0, e = r2rMap_.size(); i != e; ++i)
if (r2rMap_[i]) {
DOUT << " reg " << i << " -> ";
DEBUG(printRegName(r2rMap_[i]));
}
void SimpleRegisterCoalescing::releaseMemory() {
- r2rMap_.clear();
- JoinedLIs.clear();
- SubRegIdxes.clear();
+ for (unsigned i = 0, e = r2rMap_.size(); i != e; ++i)
+ r2rRevMap_[i].clear();
+ r2rRevMap_.clear();
+ r2rMap_.clear();
+ JoinedLIs.clear();
+ SubRegIdxes.clear();
}
static bool isZeroLengthInterval(LiveInterval *li) {
SSARegMap *RegMap = mf_->getSSARegMap();
r2rMap_.grow(RegMap->getLastVirtReg());
+ r2rRevMap_.grow(RegMap->getLastVirtReg());
// Join (coalesce) intervals if requested.
if (EnableJoining) {
DOUT << "\n";
}
- // Track coalesced sub-registers.
+ // Transfer sub-registers info to SSARegMap now that coalescing information
+ // is complete.
while (!SubRegIdxes.empty()) {
std::pair<unsigned, unsigned> RI = SubRegIdxes.back();
SubRegIdxes.pop_back();
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