Make load->store deletion a bit smarter. This allows us to compile this:

[oota-llvm.git] / lib / CodeGen / SimpleRegisterCoalescing.h

diff --git a/lib/CodeGen/SimpleRegisterCoalescing.h b/lib/CodeGen/SimpleRegisterCoalescing.h
index 2665a3ad7153df7a7292491be6c781a4988394b2..575ea57ac574dccbfa8e5732fe9f6583bbccece3 100644 (file)
--- a/lib/CodeGen/SimpleRegisterCoalescing.h
+++ b/lib/CodeGen/SimpleRegisterCoalescing.h
@@ -2,8 +2,8 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
@@ -28,7 +28,7 @@ namespace llvm {
   class MRegisterInfo;
   class TargetInstrInfo;
   class VirtRegMap;
-  class LoopInfo;
+  class MachineLoopInfo;
 
   /// CopyRec - Representation for copy instructions in coalescer queue.
   ///
@@ -48,7 +48,7 @@ namespace llvm {
   ///
   struct CopyRecSort : public std::binary_function<CopyRec,CopyRec,bool> {
     JoinPriorityQueue<CopyRecSort> *JPQ;
-    CopyRecSort(JoinPriorityQueue<CopyRecSort> *jpq) : JPQ(jpq) {}
+    explicit CopyRecSort(JoinPriorityQueue<CopyRecSort> *jpq) : JPQ(jpq) {}
     CopyRecSort(const CopyRecSort &RHS) : JPQ(RHS.JPQ) {}
     bool operator()(CopyRec left, CopyRec right) const;
   };
@@ -61,7 +61,8 @@ namespace llvm {
     std::priority_queue<CopyRec, std::vector<CopyRec>, SF> Queue;
 
   public:
-    JoinPriorityQueue(SimpleRegisterCoalescing *rc) : Rc(rc), Queue(SF(this)) {}
+    explicit JoinPriorityQueue(SimpleRegisterCoalescing *rc)
+      : Rc(rc), Queue(SF(this)) {}
 
     bool empty() const { return Queue.empty(); }
     void push(CopyRec R) { Queue.push(R); }
@@ -84,7 +85,7 @@ namespace llvm {
     const TargetInstrInfo* tii_;
     LiveIntervals *li_;
     LiveVariables *lv_;
-    const LoopInfo* loopInfo;
+    const MachineLoopInfo* loopInfo;
     
     BitVector allocatableRegs_;
     DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs_;