#include "Spiller.h"
#include "VirtRegMap.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
-#include "llvm/CodeGen/LiveStackAnalysis.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
+namespace {
+ enum SpillerName { trivial, standard };
+}
+
+static cl::opt<SpillerName>
+spillerOpt("spiller",
+ cl::desc("Spiller to use: (default: standard)"),
+ cl::Prefix,
+ cl::values(clEnumVal(trivial, "trivial spiller"),
+ clEnumVal(standard, "default spiller"),
+ clEnumValEnd),
+ cl::init(standard));
+
Spiller::~Spiller() {}
namespace {
MachineFunction *mf;
LiveIntervals *lis;
- LiveStacks *ls;
MachineFrameInfo *mfi;
MachineRegisterInfo *mri;
const TargetInstrInfo *tii;
VirtRegMap *vrm;
/// Construct a spiller base.
- SpillerBase(MachineFunction *mf, LiveIntervals *lis, LiveStacks *ls,
- VirtRegMap *vrm) :
- mf(mf), lis(lis), ls(ls), vrm(vrm)
+ SpillerBase(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm)
+ : mf(mf), lis(lis), vrm(vrm)
{
mfi = mf->getFrameInfo();
mri = &mf->getRegInfo();
tii = mf->getTarget().getInstrInfo();
}
- /// Ensures there is space before the given machine instruction, returns the
- /// instruction's new number.
- unsigned makeSpaceBefore(MachineInstr *mi) {
- if (!lis->hasGapBeforeInstr(lis->getInstructionIndex(mi))) {
- lis->scaleNumbering(2);
- ls->scaleNumbering(2);
- }
-
- unsigned miIdx = lis->getInstructionIndex(mi);
-
- assert(lis->hasGapBeforeInstr(miIdx));
-
- return miIdx;
- }
-
- /// Ensure there is space after the given machine instruction, returns the
- /// instruction's new number.
- unsigned makeSpaceAfter(MachineInstr *mi) {
- if (!lis->hasGapAfterInstr(lis->getInstructionIndex(mi))) {
- lis->scaleNumbering(2);
- ls->scaleNumbering(2);
- }
-
- unsigned miIdx = lis->getInstructionIndex(mi);
-
- assert(lis->hasGapAfterInstr(miIdx));
-
- return miIdx;
- }
-
- /// Insert a store of the given vreg to the given stack slot immediately
- /// after the given instruction. Returns the base index of the inserted
- /// instruction. The caller is responsible for adding an appropriate
- /// LiveInterval to the LiveIntervals analysis.
- unsigned insertStoreAfter(MachineInstr *mi, unsigned ss,
- unsigned vreg,
- const TargetRegisterClass *trc) {
-
- MachineBasicBlock::iterator nextInstItr(next(mi));
-
- unsigned miIdx = makeSpaceAfter(mi);
-
- tii->storeRegToStackSlot(*mi->getParent(), nextInstItr, vreg,
- true, ss, trc);
- MachineBasicBlock::iterator storeInstItr(next(mi));
- MachineInstr *storeInst = &*storeInstItr;
- unsigned storeInstIdx = miIdx + LiveInterval::InstrSlots::NUM;
-
- assert(lis->getInstructionFromIndex(storeInstIdx) == 0 &&
- "Store inst index already in use.");
-
- lis->InsertMachineInstrInMaps(storeInst, storeInstIdx);
-
- return storeInstIdx;
- }
-
- /// Insert a store of the given vreg to the given stack slot immediately
- /// before the given instructnion. Returns the base index of the inserted
- /// Instruction.
- unsigned insertStoreBefore(MachineInstr *mi, unsigned ss,
- unsigned vreg,
- const TargetRegisterClass *trc) {
- unsigned miIdx = makeSpaceBefore(mi);
-
- tii->storeRegToStackSlot(*mi->getParent(), mi, vreg, true, ss, trc);
- MachineBasicBlock::iterator storeInstItr(prior(mi));
- MachineInstr *storeInst = &*storeInstItr;
- unsigned storeInstIdx = miIdx - LiveInterval::InstrSlots::NUM;
-
- assert(lis->getInstructionFromIndex(storeInstIdx) == 0 &&
- "Store inst index already in use.");
-
- lis->InsertMachineInstrInMaps(storeInst, storeInstIdx);
-
- return storeInstIdx;
- }
-
- void insertStoreAfterInstOnInterval(LiveInterval *li,
- MachineInstr *mi, unsigned ss,
- unsigned vreg,
- const TargetRegisterClass *trc) {
-
- unsigned storeInstIdx = insertStoreAfter(mi, ss, vreg, trc);
- unsigned start = lis->getDefIndex(lis->getInstructionIndex(mi)),
- end = lis->getUseIndex(storeInstIdx);
-
- VNInfo *vni =
- li->getNextValue(storeInstIdx, 0, true, lis->getVNInfoAllocator());
- li->addKill(vni, storeInstIdx, false);
- DEBUG(errs() << " Inserting store range: [" << start
- << ", " << end << ")\n");
- LiveRange lr(start, end, vni);
-
- li->addRange(lr);
- }
-
- /// Insert a load of the given vreg from the given stack slot immediately
- /// after the given instruction. Returns the base index of the inserted
- /// instruction. The caller is responsibel for adding/removing an appropriate
- /// range vreg's LiveInterval.
- unsigned insertLoadAfter(MachineInstr *mi, unsigned ss,
- unsigned vreg,
- const TargetRegisterClass *trc) {
-
- MachineBasicBlock::iterator nextInstItr(next(mi));
-
- unsigned miIdx = makeSpaceAfter(mi);
-
- tii->loadRegFromStackSlot(*mi->getParent(), nextInstItr, vreg, ss, trc);
- MachineBasicBlock::iterator loadInstItr(next(mi));
- MachineInstr *loadInst = &*loadInstItr;
- unsigned loadInstIdx = miIdx + LiveInterval::InstrSlots::NUM;
-
- assert(lis->getInstructionFromIndex(loadInstIdx) == 0 &&
- "Store inst index already in use.");
-
- lis->InsertMachineInstrInMaps(loadInst, loadInstIdx);
-
- return loadInstIdx;
- }
-
- /// Insert a load of the given vreg from the given stack slot immediately
- /// before the given instruction. Returns the base index of the inserted
- /// instruction. The caller is responsible for adding an appropriate
- /// LiveInterval to the LiveIntervals analysis.
- unsigned insertLoadBefore(MachineInstr *mi, unsigned ss,
- unsigned vreg,
- const TargetRegisterClass *trc) {
- unsigned miIdx = makeSpaceBefore(mi);
-
- tii->loadRegFromStackSlot(*mi->getParent(), mi, vreg, ss, trc);
- MachineBasicBlock::iterator loadInstItr(prior(mi));
- MachineInstr *loadInst = &*loadInstItr;
- unsigned loadInstIdx = miIdx - LiveInterval::InstrSlots::NUM;
-
- assert(lis->getInstructionFromIndex(loadInstIdx) == 0 &&
- "Load inst index already in use.");
-
- lis->InsertMachineInstrInMaps(loadInst, loadInstIdx);
-
- return loadInstIdx;
- }
-
- void insertLoadBeforeInstOnInterval(LiveInterval *li,
- MachineInstr *mi, unsigned ss,
- unsigned vreg,
- const TargetRegisterClass *trc) {
-
- unsigned loadInstIdx = insertLoadBefore(mi, ss, vreg, trc);
- unsigned start = lis->getDefIndex(loadInstIdx),
- end = lis->getUseIndex(lis->getInstructionIndex(mi));
-
- VNInfo *vni =
- li->getNextValue(loadInstIdx, 0, true, lis->getVNInfoAllocator());
- li->addKill(vni, lis->getInstructionIndex(mi), false);
- DEBUG(errs() << " Intserting load range: [" << start
- << ", " << end << ")\n");
- LiveRange lr(start, end, vni);
-
- li->addRange(lr);
- }
-
-
-
/// Add spill ranges for every use/def of the live interval, inserting loads
- /// immediately before each use, and stores after each def. No folding is
- /// attempted.
+ /// immediately before each use, and stores after each def. No folding or
+ /// remat is attempted.
std::vector<LiveInterval*> trivialSpillEverywhere(LiveInterval *li) {
DEBUG(errs() << "Spilling everywhere " << *li << "\n");
const TargetRegisterClass *trc = mri->getRegClass(li->reg);
unsigned ss = vrm->assignVirt2StackSlot(li->reg);
+ // Iterate over reg uses/defs.
for (MachineRegisterInfo::reg_iterator
regItr = mri->reg_begin(li->reg); regItr != mri->reg_end();) {
+ // Grab the use/def instr.
MachineInstr *mi = &*regItr;
DEBUG(errs() << " Processing " << *mi);
+ // Step regItr to the next use/def instr.
do {
++regItr;
} while (regItr != mri->reg_end() && (&*regItr == mi));
+ // Collect uses & defs for this instr.
SmallVector<unsigned, 2> indices;
bool hasUse = false;
bool hasDef = false;
-
for (unsigned i = 0; i != mi->getNumOperands(); ++i) {
MachineOperand &op = mi->getOperand(i);
-
if (!op.isReg() || op.getReg() != li->reg)
continue;
-
hasUse |= mi->getOperand(i).isUse();
hasDef |= mi->getOperand(i).isDef();
-
indices.push_back(i);
}
+ // Create a new vreg & interval for this instr.
unsigned newVReg = mri->createVirtualRegister(trc);
vrm->grow();
vrm->assignVirt2StackSlot(newVReg, ss);
-
LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
newLI->weight = HUGE_VALF;
+ // Update the reg operands & kill flags.
for (unsigned i = 0; i < indices.size(); ++i) {
- mi->getOperand(indices[i]).setReg(newVReg);
-
- if (mi->getOperand(indices[i]).isUse()) {
- mi->getOperand(indices[i]).setIsKill(true);
+ unsigned mopIdx = indices[i];
+ MachineOperand &mop = mi->getOperand(mopIdx);
+ mop.setReg(newVReg);
+ if (mop.isUse() && !mi->isRegTiedToDefOperand(mopIdx)) {
+ mop.setIsKill(true);
}
}
-
assert(hasUse || hasDef);
+ // Insert reload if necessary.
+ MachineBasicBlock::iterator miItr(mi);
if (hasUse) {
- insertLoadBeforeInstOnInterval(newLI, mi, ss, newVReg, trc);
+ tii->loadRegFromStackSlot(*mi->getParent(), miItr, newVReg, ss, trc);
+ MachineInstr *loadInstr(prior(miItr));
+ SlotIndex loadIndex =
+ lis->InsertMachineInstrInMaps(loadInstr).getDefIndex();
+ SlotIndex endIndex = loadIndex.getNextIndex();
+ VNInfo *loadVNI =
+ newLI->getNextValue(loadIndex, 0, true, lis->getVNInfoAllocator());
+ loadVNI->addKill(endIndex);
+ newLI->addRange(LiveRange(loadIndex, endIndex, loadVNI));
}
+ // Insert store if necessary.
if (hasDef) {
- insertStoreAfterInstOnInterval(newLI, mi, ss, newVReg, trc);
+ tii->storeRegToStackSlot(*mi->getParent(), llvm::next(miItr), newVReg, true,
+ ss, trc);
+ MachineInstr *storeInstr(llvm::next(miItr));
+ SlotIndex storeIndex =
+ lis->InsertMachineInstrInMaps(storeInstr).getDefIndex();
+ SlotIndex beginIndex = storeIndex.getPrevIndex();
+ VNInfo *storeVNI =
+ newLI->getNextValue(beginIndex, 0, true, lis->getVNInfoAllocator());
+ storeVNI->addKill(storeIndex);
+ newLI->addRange(LiveRange(beginIndex, storeIndex, storeVNI));
}
added.push_back(newLI);
class TrivialSpiller : public SpillerBase {
public:
- TrivialSpiller(MachineFunction *mf, LiveIntervals *lis, LiveStacks *ls,
- VirtRegMap *vrm) :
- SpillerBase(mf, lis, ls, vrm) {}
+ TrivialSpiller(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm)
+ : SpillerBase(mf, lis, vrm) {}
- std::vector<LiveInterval*> spill(LiveInterval *li) {
+ std::vector<LiveInterval*> spill(LiveInterval *li,
+ SmallVectorImpl<LiveInterval*> &spillIs) {
+ // Ignore spillIs - we don't use it.
return trivialSpillEverywhere(li);
}
- std::vector<LiveInterval*> intraBlockSplit(LiveInterval *li, VNInfo *valno) {
- std::vector<LiveInterval*> spillIntervals;
-
- if (!valno->isDefAccurate() && !valno->isPHIDef()) {
- // Early out for values which have no well defined def point.
- return spillIntervals;
- }
-
- // Ok.. we should be able to proceed...
- const TargetRegisterClass *trc = mri->getRegClass(li->reg);
- unsigned ss = vrm->assignVirt2StackSlot(li->reg);
- vrm->grow();
- vrm->assignVirt2StackSlot(li->reg, ss);
-
- MachineInstr *mi = 0;
- unsigned storeIdx = 0;
-
- if (valno->isDefAccurate()) {
- // If we have an accurate def we can just grab an iterator to the instr
- // after the def.
- mi = lis->getInstructionFromIndex(valno->def);
- storeIdx = insertStoreAfter(mi, ss, li->reg, trc) +
- LiveInterval::InstrSlots::DEF;
- } else {
- // if we get here we have a PHI def.
- mi = &lis->getMBBFromIndex(valno->def)->front();
- storeIdx = insertStoreBefore(mi, ss, li->reg, trc) +
- LiveInterval::InstrSlots::DEF;
- }
-
- MachineBasicBlock *defBlock = mi->getParent();
- unsigned loadIdx = 0;
-
- // Now we need to find the load...
- MachineBasicBlock::iterator useItr(mi);
- for (; !useItr->readsRegister(li->reg); ++useItr) {}
-
- if (useItr != defBlock->end()) {
- MachineInstr *loadInst = useItr;
- loadIdx = insertLoadBefore(loadInst, ss, li->reg, trc) +
- LiveInterval::InstrSlots::USE;
- }
- else {
- MachineInstr *loadInst = &defBlock->back();
- loadIdx = insertLoadAfter(loadInst, ss, li->reg, trc) +
- LiveInterval::InstrSlots::USE;
- }
-
- li->removeRange(storeIdx, loadIdx, true);
+};
- return spillIntervals;
+/// Falls back on LiveIntervals::addIntervalsForSpills.
+class StandardSpiller : public Spiller {
+private:
+ LiveIntervals *lis;
+ const MachineLoopInfo *loopInfo;
+ VirtRegMap *vrm;
+public:
+ StandardSpiller(MachineFunction *mf, LiveIntervals *lis,
+ const MachineLoopInfo *loopInfo, VirtRegMap *vrm)
+ : lis(lis), loopInfo(loopInfo), vrm(vrm) {}
+
+ /// Falls back on LiveIntervals::addIntervalsForSpills.
+ std::vector<LiveInterval*> spill(LiveInterval *li,
+ SmallVectorImpl<LiveInterval*> &spillIs) {
+ return lis->addIntervalsForSpills(*li, spillIs, loopInfo, *vrm);
}
};
}
llvm::Spiller* llvm::createSpiller(MachineFunction *mf, LiveIntervals *lis,
- LiveStacks *ls, VirtRegMap *vrm) {
- return new TrivialSpiller(mf, lis, ls, vrm);
+ const MachineLoopInfo *loopInfo,
+ VirtRegMap *vrm) {
+ switch (spillerOpt) {
+ case trivial: return new TrivialSpiller(mf, lis, vrm); break;
+ case standard: return new StandardSpiller(mf, lis, loopInfo, vrm); break;
+ default: llvm_unreachable("Unreachable!"); break;
+ }
}
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