Fix up instruction classes for Thumb2 RSB instructions to be consistent with

[oota-llvm.git] / lib / CodeGen / StrongPHIElimination.cpp

diff --git a/lib/CodeGen/StrongPHIElimination.cpp b/lib/CodeGen/StrongPHIElimination.cpp
index f8f6a55e9df62ff70aaae7bf5ab375e788730021..142398cc16424a2d805cb1393fefd8e3c79aebf4 100644 (file)
--- a/lib/CodeGen/StrongPHIElimination.cpp
+++ b/lib/CodeGen/StrongPHIElimination.cpp
@@ -696,7 +696,7 @@ void StrongPHIElimination::ScheduleCopies(MachineBasicBlock* MBB,
         // the Phi defining curr.second
         MachineBasicBlock::iterator PI = MRI.getVRegDef(curr.second);
         TII->copyRegToReg(*PI->getParent(), PI, t,
-                          curr.second, RC, RC);
+                          curr.second, RC, RC, DebugLoc());
         
         DEBUG(dbgs() << "Inserted copy from " << curr.second << " to " << t
                      << "\n");
@@ -713,7 +713,7 @@ void StrongPHIElimination::ScheduleCopies(MachineBasicBlock* MBB,
       
       // Insert copy from map[curr.first] to curr.second
       TII->copyRegToReg(*MBB, MBB->getFirstTerminator(), curr.second,
-                        map[curr.first], RC, RC);
+                        map[curr.first], RC, RC, DebugLoc());
       map[curr.first] = curr.second;
       DEBUG(dbgs() << "Inserted copy from " << curr.first << " to "
                    << curr.second << "\n");
@@ -762,7 +762,7 @@ void StrongPHIElimination::ScheduleCopies(MachineBasicBlock* MBB,
         // Insert a copy from dest to a new temporary t at the end of b
         unsigned t = MF->getRegInfo().createVirtualRegister(RC);
         TII->copyRegToReg(*MBB, MBB->getFirstTerminator(), t,
-                          curr.second, RC, RC);
+                          curr.second, RC, RC, DebugLoc());
         map[curr.second] = t;
         
         MachineBasicBlock::iterator TI = MBB->getFirstTerminator();
@@ -961,7 +961,7 @@ bool StrongPHIElimination::runOnMachineFunction(MachineFunction &Fn) {
           const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
           const TargetRegisterClass *RC = Fn.getRegInfo().getRegClass(I->first);
           TII->copyRegToReg(*SI->second, SI->second->getFirstTerminator(),
-                            I->first, SI->first, RC, RC);
+                            I->first, SI->first, RC, RC, DebugLoc());
           
           LI.renumber();