// Waiting stores, for each MBB, the set of copies that need to
// be inserted into that MBB
DenseMap<MachineBasicBlock*,
- std::map<unsigned, unsigned> > Waiting;
+ std::multimap<unsigned, unsigned> > Waiting;
// Stacks holds the renaming stack for each register
std::map<unsigned, std::vector<unsigned> > Stacks;
LiveIntervals& LI) {
LiveInterval& I = LI.getOrCreateInterval(r);
unsigned idx = LI.getMBBStartIdx(MBB);
- return I.liveBeforeAndAt(idx);
+ return I.liveAt(idx);
}
/// isLiveOut - help method that determines, from a regno, if a register is
MachineBasicBlock::iterator P = MBB->begin();
while (P != MBB->end() && P->getOpcode() == TargetInstrInfo::PHI) {
unsigned DestReg = P->getOperand(0).getReg();
-
// Don't both doing PHI elimination for dead PHI's.
if (P->registerDefIsDead(DestReg)) {
ProcessedNames.insert(SrcReg);
continue;
}
+
+ // We don't need to insert copies for implicit_defs.
+ MachineInstr* DefMI = MRI.getVRegDef(SrcReg);
+ if (DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
+ ProcessedNames.insert(SrcReg);
// Check for trivial interferences via liveness information, allowing us
// to avoid extra work later. Any registers that interfere cannot both
void StrongPHIElimination::ScheduleCopies(MachineBasicBlock* MBB,
std::set<unsigned>& pushed) {
// FIXME: This function needs to update LiveIntervals
- std::map<unsigned, unsigned>& copy_set= Waiting[MBB];
+ std::multimap<unsigned, unsigned>& copy_set= Waiting[MBB];
- std::map<unsigned, unsigned> worklist;
+ std::multimap<unsigned, unsigned> worklist;
std::map<unsigned, unsigned> map;
// Setup worklist of initial copies
- for (std::map<unsigned, unsigned>::iterator I = copy_set.begin(),
+ for (std::multimap<unsigned, unsigned>::iterator I = copy_set.begin(),
E = copy_set.end(); I != E; ) {
map.insert(std::make_pair(I->first, I->first));
map.insert(std::make_pair(I->second, I->second));
worklist.insert(*I);
// Avoid iterator invalidation
- unsigned first = I->first;
+ std::multimap<unsigned, unsigned>::iterator OI = I;
++I;
- copy_set.erase(first);
+ copy_set.erase(OI);
} else {
++I;
}
// Iterate over the worklist, inserting copies
while (!worklist.empty() || !copy_set.empty()) {
while (!worklist.empty()) {
- std::pair<unsigned, unsigned> curr = *worklist.begin();
- worklist.erase(curr.first);
+ std::multimap<unsigned, unsigned>::iterator WI = worklist.begin();
+ std::pair<unsigned, unsigned> curr = *WI;
+ worklist.erase(WI);
const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(curr.first);
TII->copyRegToReg(*PI->getParent(), PI, t,
curr.second, RC, RC);
+ DOUT << "Inserted copy from " << curr.second << " to " << t << "\n";
+
// Push temporary on Stacks
Stacks[curr.second].push_back(t);
TII->copyRegToReg(*MBB, MBB->getFirstTerminator(), curr.second,
map[curr.first], RC, RC);
map[curr.first] = curr.second;
+ DOUT << "Inserted copy from " << curr.first << " to "
+ << curr.second << "\n";
// Push this copy onto InsertedPHICopies so we can
// update LiveIntervals with it.
InsertedPHIDests.push_back(std::make_pair(curr.second, --MI));
// If curr.first is a destination in copy_set...
- for (std::map<unsigned, unsigned>::iterator I = copy_set.begin(),
+ for (std::multimap<unsigned, unsigned>::iterator I = copy_set.begin(),
E = copy_set.end(); I != E; )
if (curr.first == I->second) {
std::pair<unsigned, unsigned> temp = *I;
+ worklist.insert(temp);
// Avoid iterator invalidation
+ std::multimap<unsigned, unsigned>::iterator OI = I;
++I;
- copy_set.erase(temp.first);
- worklist.insert(temp);
+ copy_set.erase(OI);
break;
} else {
}
if (!copy_set.empty()) {
- std::pair<unsigned, unsigned> curr = *copy_set.begin();
- copy_set.erase(curr.first);
+ std::multimap<unsigned, unsigned>::iterator CI = copy_set.begin();
+ std::pair<unsigned, unsigned> curr = *CI;
worklist.insert(curr);
+ copy_set.erase(CI);
LiveInterval& I = LI.getInterval(curr.second);
MachineBasicBlock::iterator term = MBB->getFirstTerminator();
continue;
for (unsigned i = 0; i < I->getNumOperands(); ++i)
- if (I->getOperand(i).isRegister() &&
+ if (I->getOperand(i).isReg() &&
Stacks[I->getOperand(i).getReg()].size()) {
// Remove the live range for the old vreg.
LiveInterval& OldInt = LI.getInterval(I->getOperand(i).getReg());
}
}
+ LiveInterval& Int = LI.getOrCreateInterval(I->first);
+ const LiveRange* LR =
+ Int.getLiveRangeContaining(LI.getMBBEndIdx(SI->second));
+ LR->valno->hasPHIKill = true;
+
I->second.erase(SI->first);
}