[X86][Haswell][SchedModel] Tidy up.

[oota-llvm.git] / lib / CodeGen / TargetInstrInfo.cpp

diff --git a/lib/CodeGen/TargetInstrInfo.cpp b/lib/CodeGen/TargetInstrInfo.cpp
index 8c57beb5ee9583b54c6ba0d0a6370255e4dc2ac6..44fbc4bb63124f5ce086438ff5b43af116c00345 100644 (file)
--- a/lib/CodeGen/TargetInstrInfo.cpp
+++ b/lib/CodeGen/TargetInstrInfo.cpp
@@ -856,8 +856,8 @@ computeOperandLatency(const InstrItineraryData *ItinData,
 bool TargetInstrInfo::getRegSequenceInputs(
     const MachineInstr &MI, unsigned DefIdx,
     SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
-  assert(MI.isRegSequence() ||
-         MI.isRegSequenceLike() && "Instruction do not have the proper type");
+  assert((MI.isRegSequence() ||
+          MI.isRegSequenceLike()) && "Instruction do not have the proper type");
 
   if (!MI.isRegSequence())
     return getRegSequenceLikeInputs(MI, DefIdx, InputRegs);