Implement vector shift up / down and insert zero with ps{rl}lq / ps{rl}ldq.

[oota-llvm.git] / lib / CodeGen / TargetInstrInfoImpl.cpp

diff --git a/lib/CodeGen/TargetInstrInfoImpl.cpp b/lib/CodeGen/TargetInstrInfoImpl.cpp
index 4f6c1237e9f8889ab5533a6309543436e756bb85..1bb08ab93bb20926527e8f5b6fd314b180efff3e 100644 (file)
--- a/lib/CodeGen/TargetInstrInfoImpl.cpp
+++ b/lib/CodeGen/TargetInstrInfoImpl.cpp
@@ -39,8 +39,28 @@ MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI) const {
   return MI;
 }
 
+/// CommuteChangesDestination - Return true if commuting the specified
+/// instruction will also changes the destination operand. Also return the
+/// current operand index of the would be new destination register by
+/// reference. This can happen when the commutable instruction is also a
+/// two-address instruction.
+bool TargetInstrInfoImpl::CommuteChangesDestination(MachineInstr *MI,
+                                                    unsigned &OpIdx) const{
+  assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
+         "This only knows how to commute register operands so far");
+  if (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
+    // Must be two address instruction!
+    assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
+           "Expecting a two-address instruction!");
+    OpIdx = 2;
+    return true;
+  }
+  return false;
+}
+
+
 bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
-                                               const std::vector<MachineOperand> &Pred) const {
+                                const std::vector<MachineOperand> &Pred) const {
   bool MadeChange = false;
   const TargetInstrDesc &TID = MI->getDesc();
   if (!TID.isPredicable())
@@ -64,3 +84,24 @@ bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
   }
   return MadeChange;
 }
+
+void TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB,
+                                        MachineBasicBlock::iterator I,
+                                        unsigned DestReg,
+                                        const MachineInstr *Orig) const {
+  MachineInstr *MI = Orig->clone();
+  MI->getOperand(0).setReg(DestReg);
+  MBB.insert(I, MI);
+}
+
+unsigned
+TargetInstrInfoImpl::GetFunctionSizeInBytes(const MachineFunction &MF) const {
+  unsigned FnSize = 0;
+  for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
+       MBBI != E; ++MBBI) {
+    const MachineBasicBlock &MBB = *MBBI;
+    for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end(); I != E; ++I)
+      FnSize += GetInstSizeInBytes(I);
+  }
+  return FnSize;
+}