AU.addPreserved<LiveVariables>();
AU.addPreservedID(MachineLoopInfoID);
AU.addPreservedID(MachineDominatorsID);
- AU.addPreservedID(PHIEliminationID);
MachineFunctionPass::getAnalysisUsage(AU);
}
// If any of the definitions are used by another instruction between the
// position and the kill use, then it's not safe to sink it.
- //
+ //
// FIXME: This can be sped up if there is an easy way to query whether an
// instruction is before or after another instruction. Then we can use
// MachineRegisterInfo def / use instead.
KillMO->setIsKill(false);
KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
KillMO->setIsKill(true);
-
+
if (LV)
LV->replaceKillInstruction(SavedReg, KillMI, MI);
continue; // Current use.
OtherUse = true;
// There is at least one other use in the MBB that will clobber the
- // register.
+ // register.
if (isTwoAddrUse(UseMI, Reg))
return true;
}
// %reg1029<def> = MOV8rr %reg1028
// %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
// insert => %reg1030<def> = MOV8rr %reg1029
- // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
+ // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
if (!MI->killsRegister(regC))
return false;
MachineBasicBlock::iterator &nmi,
unsigned Reg) {
MachineInstr *MI = &*mi;
- DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
+ DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
if (DI == DistanceMap.end())
// Must be created from unfolded load. Don't waste time trying this.
return false;
if (LV) {
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
- if (MO.isReg() &&
+ if (MO.isReg() &&
TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
if (MO.isUse()) {
if (MO.isKill()) {
bool MadeChange = false;
DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
- DEBUG(dbgs() << "********** Function: "
+ DEBUG(dbgs() << "********** Function: "
<< MF.getFunction()->getName() << '\n');
// This pass takes the function out of SSA form.
}
}
+// Find the first def of Reg, assuming they are all in the same basic block.
+static MachineInstr *findFirstDef(unsigned Reg, MachineRegisterInfo *MRI) {
+ SmallPtrSet<MachineInstr*, 8> Defs;
+ MachineInstr *First = 0;
+ for (MachineRegisterInfo::def_iterator RI = MRI->def_begin(Reg);
+ MachineInstr *MI = RI.skipInstruction(); Defs.insert(MI))
+ First = MI;
+ if (!First)
+ return 0;
+
+ MachineBasicBlock *MBB = First->getParent();
+ MachineBasicBlock::iterator A = First, B = First;
+ bool Moving;
+ do {
+ Moving = false;
+ if (A != MBB->begin()) {
+ Moving = true;
+ --A;
+ if (Defs.erase(A)) First = A;
+ }
+ if (B != MBB->end()) {
+ Defs.erase(B);
+ ++B;
+ Moving = true;
+ }
+ } while (Moving && !Defs.empty());
+ assert(Defs.empty() && "Instructions outside basic block!");
+ return First;
+}
+
/// CoalesceExtSubRegs - If a number of sources of the REG_SEQUENCE are
/// EXTRACT_SUBREG from the same register and to the same virtual register
/// with different sub-register indices, attempt to combine the
CanCoalesce = false;
break;
}
- // Keep track of one of the uses.
- SomeMI = UseMI;
+ // Keep track of one of the uses. Preferably the first one which has a
+ // <def,undef> flag.
+ if (!SomeMI || UseMI->getOperand(0).isUndef())
+ SomeMI = UseMI;
}
if (!CanCoalesce)
continue;
MachineInstr *CopyMI = BuildMI(*SomeMI->getParent(), SomeMI,
SomeMI->getDebugLoc(),
TII->get(TargetOpcode::COPY))
- .addReg(DstReg, RegState::Define, NewDstSubIdx)
+ .addReg(DstReg, RegState::Define |
+ getUndefRegState(SomeMI->getOperand(0).isUndef()),
+ NewDstSubIdx)
.addReg(SrcReg, 0, NewSrcSubIdx);
// Remove all the old extract instructions.
for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
unsigned SrcReg = MI->getOperand(i).getReg();
unsigned SubIdx = MI->getOperand(i+1).getImm();
- if (MI->getOperand(i).getSubReg() ||
- TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
- DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
- llvm_unreachable(0);
+ // DefMI of NULL means the value does not have a vreg in this block
+ // i.e., its a physical register or a subreg.
+ // In either case we force a copy to be generated.
+ MachineInstr *DefMI = NULL;
+ if (!MI->getOperand(i).getSubReg() &&
+ !TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
+ DefMI = MRI->getVRegDef(SrcReg);
}
- MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
- if (DefMI->isImplicitDef()) {
+ if (DefMI && DefMI->isImplicitDef()) {
DefMI->eraseFromParent();
continue;
}
IsImpDef = false;
// Remember COPY sources. These might be candidate for coalescing.
- if (DefMI->isCopy() && DefMI->getOperand(1).getSubReg())
+ if (DefMI && DefMI->isCopy() && DefMI->getOperand(1).getSubReg())
RealSrcs.push_back(DefMI->getOperand(1).getReg());
bool isKill = MI->getOperand(i).isKill();
- if (!Seen.insert(SrcReg) || MI->getParent() != DefMI->getParent() ||
+ if (!DefMI || !Seen.insert(SrcReg) ||
+ MI->getParent() != DefMI->getParent() ||
!isKill || HasOtherRegSequenceUses(SrcReg, MI, MRI) ||
!TRI->getMatchingSuperRegClass(MRI->getRegClass(DstReg),
MRI->getRegClass(SrcReg), SubIdx)) {
.addReg(DstReg, RegState::Define, SubIdx)
.addReg(SrcReg, getKillRegState(isKill));
MI->getOperand(i).setReg(0);
- if (LV && isKill)
+ if (LV && isKill && !TargetRegisterInfo::isPhysicalRegister(SrcReg))
LV->replaceKillInstruction(SrcReg, MI, CopyMI);
DEBUG(dbgs() << "Inserted: " << *CopyMI);
}
UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI, *TRI);
}
+ // Set <def,undef> flags on the first DstReg def in the basic block.
+ // It marks the beginning of the live range. All the other defs are
+ // read-modify-write.
+ if (MachineInstr *Def = findFirstDef(DstReg, MRI)) {
+ for (unsigned i = 0, e = Def->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = Def->getOperand(i);
+ if (MO.isReg() && MO.isDef() && MO.getReg() == DstReg)
+ MO.setIsUndef();
+ }
+ // Make sure there is a full non-subreg imp-def operand on the
+ // instruction. This shouldn't be necessary, but it seems that at least
+ // RAFast requires it.
+ Def->addRegisterDefined(DstReg, TRI);
+ DEBUG(dbgs() << "First def: " << *Def);
+ }
+
if (IsImpDef) {
DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF");
MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
- MI->RemoveOperand(j);
+ MI->RemoveOperand(j);
} else {
DEBUG(dbgs() << "Eliminated: " << *MI);
MI->eraseFromParent();