#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetOptions.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/ADT/BitVector.h"
unsigned Reg,
MachineBasicBlock::iterator OldPos);
- bool isSafeToReMat(unsigned DstReg, MachineInstr *MI);
bool isProfitableToReMat(unsigned Reg, const TargetRegisterClass *RC,
MachineInstr *MI, MachineInstr *DefMI,
MachineBasicBlock *MBB, unsigned Loc,
DenseMap<MachineInstr*, unsigned> &DistanceMap);
public:
static char ID; // Pass identification, replacement for typeid
- TwoAddressInstructionPass() : MachineFunctionPass((intptr_t)&ID) {}
+ TwoAddressInstructionPass() : MachineFunctionPass(&ID) {}
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.addPreserved<LiveVariables>();
AU.addPreservedID(MachineLoopInfoID);
AU.addPreservedID(MachineDominatorsID);
- AU.addPreservedID(PHIEliminationID);
+ if (StrongPHIElim)
+ AU.addPreservedID(StrongPHIEliminationID);
+ else
+ AU.addPreservedID(PHIEliminationID);
MachineFunctionPass::getAnalysisUsage(AU);
}
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isRegister())
+ if (!MO.isReg())
continue;
unsigned MOReg = MO.getReg();
if (!MOReg)
++NumVisited;
for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = OtherMI->getOperand(i);
- if (!MO.isRegister())
+ if (!MO.isReg())
continue;
unsigned MOReg = MO.getReg();
if (!MOReg)
KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
KillMO->setIsKill(true);
- if (LV) {
- LiveVariables::VarInfo& VarInfo = LV->getVarInfo(SavedReg);
- VarInfo.removeKill(KillMI);
- VarInfo.Kills.push_back(MI);
- }
+ if (LV)
+ LV->replaceKillInstruction(SavedReg, KillMI, MI);
// Move instruction to its destination.
MBB->remove(MI);
return true;
}
-/// isSafeToReMat - Return true if it's safe to rematerialize the specified
-/// instruction which defined the specified register instead of copying it.
-bool
-TwoAddressInstructionPass::isSafeToReMat(unsigned DstReg, MachineInstr *MI) {
- const TargetInstrDesc &TID = MI->getDesc();
- if (!TID.isAsCheapAsAMove())
- return false;
- bool SawStore = false;
- if (!MI->isSafeToMove(TII, SawStore))
- return false;
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- MachineOperand &MO = MI->getOperand(i);
- if (!MO.isRegister())
- continue;
- // FIXME: For now, do not remat any instruction with register operands.
- // Later on, we can loosen the restriction is the register operands have
- // not been modified between the def and use. Note, this is different from
- // MachineSink because the code in no longer in two-address form (at least
- // partially).
- if (MO.isUse())
- return false;
- else if (!MO.isDead() && MO.getReg() != DstReg)
- return false;
- }
- return true;
-}
-
/// isTwoAddrUse - Return true if the specified MI is using the specified
/// register as a two-address operand.
static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) {
const TargetInstrDesc &TID = UseMI->getDesc();
for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
MachineOperand &MO = UseMI->getOperand(i);
- if (MO.isRegister() && MO.getReg() == Reg &&
+ if (MO.isReg() && MO.getReg() == Reg &&
(MO.isDef() || TID.getOperandConstraint(i, TOI::TIED_TO) != -1))
// Earlier use is a two-address one.
return true;
FirstTied = false;
- assert(mi->getOperand(si).isRegister() && mi->getOperand(si).getReg() &&
+ assert(mi->getOperand(si).isReg() && mi->getOperand(si).getReg() &&
mi->getOperand(si).isUse() && "two address instruction invalid");
// If the two operands are the same we just remove the use
// should never occur because we are in SSA form.
for (unsigned i = 0; i != mi->getNumOperands(); ++i)
assert((int)i == ti ||
- !mi->getOperand(i).isRegister() ||
+ !mi->getOperand(i).isReg() ||
mi->getOperand(i).getReg() != regA);
#endif
// and C joinable.
// FIXME: This code also works for A := B op C instructions.
if (TID.isCommutable() && mi->getNumOperands() >= 3) {
- assert(mi->getOperand(3-si).isRegister() &&
+ assert(mi->getOperand(3-si).isReg() &&
"Not a proper commutative instruction!");
unsigned regC = mi->getOperand(3-si).getReg();
DOUT << "2addr: COMMUTED TO: " << *NewMI;
// If the instruction changed to commute it, update livevar.
if (NewMI != mi) {
- if (LV) {
+ if (LV)
// Update live variables
- LV->instructionChanged(mi, NewMI);
- } else {
- // Update flags manually
- for (unsigned i = 0, e = mi->getNumOperands();
- i != e; ++i) {
- MachineOperand &MO = mi->getOperand(i);
- if (MO.isRegister() && MO.getReg() &&
- TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
- unsigned Reg = MO.getReg();
- if (MO.isDef()) {
- if (MO.isDead()) {
- MO.setIsDead(false);
- NewMI->addRegisterDead(Reg, TRI);
- }
- }
-
- if (MO.isKill()) {
- MO.setIsKill(false);
- NewMI->addRegisterKilled(Reg, TRI);
- }
- }
- }
- }
+ LV->replaceKillInstruction(regC, mi, NewMI);
mbbi->insert(mi, NewMI); // Insert the new inst
mbbi->erase(mi); // Nuke the old inst.
assert(TID.getOperandConstraint(i, TOI::TIED_TO) == -1);
#endif
- MachineInstr *NewMI = TII->convertToThreeAddress(mbbi, mi, *LV);
+ MachineInstr *NewMI = TII->convertToThreeAddress(mbbi, mi, LV);
if (NewMI) {
DOUT << "2addr: CONVERTING 2-ADDR: " << *mi;
DOUT << "2addr: TO 3-ADDR: " << *NewMI;
// If it's safe and profitable, remat the definition instead of
// copying it.
if (DefMI &&
- isSafeToReMat(regB, DefMI) &&
+ DefMI->getDesc().isAsCheapAsAMove() &&
+ DefMI->isSafeToReMat(TII, regB) &&
isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist,DistanceMap)){
DEBUG(cerr << "2addr: REMATTING : " << *DefMI << "\n");
TII->reMaterialize(*mbbi, mi, regA, DefMI);
}
MachineBasicBlock::iterator prevMi = prior(mi);
- DOUT << "\t\tprepend:\t"; DEBUG(prevMi->print(*cerr.stream(), &TM));
// Update live variables for regB.
if (LV) {
// regB is used in this BB.
varInfoB.UsedBlocks[mbbi->getNumber()] = true;
- if (LV->removeVirtualRegisterKilled(regB, mbbi, mi))
+ if (LV->removeVirtualRegisterKilled(regB, mi))
LV->addVirtualRegisterKilled(regB, prevMi);
- if (LV->removeVirtualRegisterDead(regB, mbbi, mi))
+ if (LV->removeVirtualRegisterDead(regB, mi))
LV->addVirtualRegisterDead(regB, prevMi);
- } else {
- // Manually update kill/dead flags.
- bool RemovedKill = false;
- bool RemovedDead = false;
- for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
- MachineOperand &MO = mi->getOperand(i);
- if (MO.isRegister() && MO.isKill() && MO.getReg() == regB) {
- MO.setIsKill(false);
- RemovedKill = true;
- break;
- }
-
- if (MO.isRegister() && MO.isDef() && MO.getReg() == regB) {
- MO.setIsDead(false);
- RemovedDead = true;
- }
-
- if (RemovedKill && RemovedDead) break;
- }
-
- if (RemovedKill)
- prevMi->addRegisterKilled(regB, TRI);
- if (RemovedDead)
- prevMi->addRegisterDead(regB, TRI);
}
+
+ DOUT << "\t\tprepend:\t"; DEBUG(prevMi->print(*cerr.stream(), &TM));
// Replace all occurences of regB with regA.
for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
- if (mi->getOperand(i).isRegister() &&
+ if (mi->getOperand(i).isReg() &&
mi->getOperand(i).getReg() == regB)
mi->getOperand(i).setReg(regA);
}
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