namespace {
struct VISIBILITY_HIDDEN TwoAddressInstructionPass
: public MachineFunctionPass {
+ static char ID; // Pass identification, replacement for typeid
+ TwoAddressInstructionPass() : MachineFunctionPass((intptr_t)&ID) {}
+
virtual void getAnalysisUsage(AnalysisUsage &AU) const;
/// runOnMachineFunction - pass entry point
bool runOnMachineFunction(MachineFunction&);
};
+ char TwoAddressInstructionPass::ID = 0;
RegisterPass<TwoAddressInstructionPass>
X("twoaddressinstruction", "Two-Address instruction pass");
}
// If this instruction is potentially convertible to a true
// three-address instruction,
- if (TID->Flags & M_CONVERTIBLE_TO_3_ADDR)
+ if (TID->Flags & M_CONVERTIBLE_TO_3_ADDR) {
// FIXME: This assumes there are no more operands which are tied
// to another register.
#ifndef NDEBUG
// Done with this instruction.
break;
}
+ }
}
InstructionRearranged:
const TargetRegisterClass* rc = MF.getSSARegMap()->getRegClass(regA);
- MRI.copyRegToReg(*mbbi, mi, regA, regB, rc);
+ MRI.copyRegToReg(*mbbi, mi, regA, regB, rc, rc);
MachineBasicBlock::iterator prevMi = prior(mi);
DOUT << "\t\tprepend:\t"; DEBUG(prevMi->print(*cerr.stream(), &TM));
LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA);
varInfo.DefInst = prevMi;
- // update live variables for regB
if (LV.removeVirtualRegisterKilled(regB, mbbi, mi))
LV.addVirtualRegisterKilled(regB, prevMi);