#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
+#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
+#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
using namespace llvm;
STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
+static cl::opt<bool>
+EnableReMat("2-addr-remat", cl::init(false), cl::Hidden,
+ cl::desc("Two-addr conversion should remat when possible."));
+
namespace {
- struct VISIBILITY_HIDDEN TwoAddressInstructionPass
- : public MachineFunctionPass {
+ class VISIBILITY_HIDDEN TwoAddressInstructionPass
+ : public MachineFunctionPass {
const TargetInstrInfo *TII;
const TargetRegisterInfo *TRI;
MachineRegisterInfo *MRI;
LiveVariables *LV;
+ bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI,
+ unsigned Reg,
+ MachineBasicBlock::iterator OldPos);
public:
static char ID; // Pass identification, replacement for typeid
TwoAddressInstructionPass() : MachineFunctionPass((intptr_t)&ID) {}
- virtual void getAnalysisUsage(AnalysisUsage &AU) const;
+ virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.addRequired<LiveVariables>();
+ AU.addPreserved<LiveVariables>();
+ AU.addPreservedID(MachineLoopInfoID);
+ AU.addPreservedID(MachineDominatorsID);
+ AU.addPreservedID(PHIEliminationID);
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
- /// runOnMachineFunction - pass entry point
+ /// runOnMachineFunction - Pass entry point.
bool runOnMachineFunction(MachineFunction&);
-
- private:
- bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI,
- unsigned Reg,
- MachineBasicBlock::iterator OldPos);
};
-
- char TwoAddressInstructionPass::ID = 0;
- RegisterPass<TwoAddressInstructionPass>
- X("twoaddressinstruction", "Two-Address instruction pass");
}
-const PassInfo *llvm::TwoAddressInstructionPassID = X.getPassInfo();
+char TwoAddressInstructionPass::ID = 0;
+static RegisterPass<TwoAddressInstructionPass>
+X("twoaddressinstruction", "Two-Address instruction pass");
-void TwoAddressInstructionPass::getAnalysisUsage(AnalysisUsage &AU) const {
- AU.addRequired<LiveVariables>();
- AU.addPreserved<LiveVariables>();
- AU.addPreservedID(MachineLoopInfoID);
- AU.addPreservedID(MachineDominatorsID);
- AU.addPreservedID(PHIEliminationID);
- MachineFunctionPass::getAnalysisUsage(AU);
-}
+const PassInfo *const llvm::TwoAddressInstructionPassID = &X;
/// Sink3AddrInstruction - A two-address instruction has been converted to a
/// three-address instruction to avoid clobbering a register. Try to sink it
-/// past the instruction that would kill the above mentioned register to
-/// reduce register pressure.
+/// past the instruction that would kill the above mentioned register to reduce
+/// register pressure.
+///
bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB,
MachineInstr *MI, unsigned SavedReg,
MachineBasicBlock::iterator OldPos) {
unsigned DefReg = 0;
SmallSet<unsigned, 4> UseRegs;
+
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isRegister())
// Find the instruction that kills SavedReg.
MachineInstr *KillMI = NULL;
+
for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SavedReg),
UE = MRI->use_end(); UI != UE; ++UI) {
MachineOperand &UseMO = UI.getOperand();
KillMI = UseMO.getParent();
break;
}
+
if (!KillMI || KillMI->getParent() != MBB)
return false;
- // If any of the definitions are used by another instruction between
- // the position and the kill use, then it's not safe to sink it.
- // FIXME: This can be sped up if there is an easy way to query whether
- // an instruction if before or after another instruction. Then we can
- // use MachineRegisterInfo def / use instead.
+ // If any of the definitions are used by another instruction between the
+ // position and the kill use, then it's not safe to sink it.
+ //
+ // FIXME: This can be sped up if there is an easy way to query whether an
+ // instruction if before or after another instruction. Then we can use
+ // MachineRegisterInfo def / use instead.
MachineOperand *KillMO = NULL;
MachineBasicBlock::iterator KillPos = KillMI;
++KillPos;
+
for (MachineBasicBlock::iterator I = next(OldPos); I != KillPos; ++I) {
MachineInstr *OtherMI = I;
+
for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = OtherMI->getOperand(i);
if (!MO.isRegister())
continue;
if (DefReg == MOReg)
return false;
+
if (MO.isKill()) {
if (OtherMI == KillMI && MOReg == SavedReg)
// Save the operand that kills the register. We want unset the kill
return true;
}
-/// runOnMachineFunction - Reduce two-address instructions to two
-/// operands.
+/// runOnMachineFunction - Reduce two-address instructions to two operands.
///
bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
DOUT << "Machine Function\n";
DOUT << "********** REWRITING TWO-ADDR INSTRS **********\n";
DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
+ SmallPtrSet<MachineInstr*, 8> ReMattedInstrs;
+
for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
mbbi != mbbe; ++mbbi) {
for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
mi != me; ) {
MachineBasicBlock::iterator nmi = next(mi);
const TargetInstrDesc &TID = mi->getDesc();
-
bool FirstTied = true;
+
for (unsigned si = 1, e = TID.getNumOperands(); si < e; ++si) {
int ti = TID.getOperandConstraint(si, TOI::TIED_TO);
if (ti == -1)
++NumTwoAddressInstrs;
DOUT << '\t'; DEBUG(mi->print(*cerr.stream(), &TM));
}
+
FirstTied = false;
assert(mi->getOperand(si).isRegister() && mi->getOperand(si).getReg() &&
mi->getOperand(si).isUse() && "two address instruction invalid");
- // if the two operands are the same we just remove the use
+ // If the two operands are the same we just remove the use
// and mark the def as def&use, otherwise we have to insert a copy.
if (mi->getOperand(ti).getReg() != mi->getOperand(si).getReg()) {
- // rewrite:
+ // Rewrite:
// a = b op c
// to:
// a = b
assert(mi->getOperand(3-si).isRegister() &&
"Not a proper commutative instruction!");
unsigned regC = mi->getOperand(3-si).getReg();
+
if (mi->killsRegister(regC)) {
DOUT << "2addr: COMMUTING : " << *mi;
MachineInstr *NewMI = TII->commuteInstruction(mi);
+
if (NewMI == 0) {
DOUT << "2addr: COMMUTING FAILED!\n";
} else {
// FIXME: This assumes there are no more operands which are tied
// to another register.
#ifndef NDEBUG
- for (unsigned i = si+1, e = TID.getNumOperands(); i < e; ++i)
+ for (unsigned i = si + 1, e = TID.getNumOperands(); i < e; ++i)
assert(TID.getOperandConstraint(i, TOI::TIED_TO) == -1);
#endif
DOUT << "2addr: CONVERTING 2-ADDR: " << *mi;
DOUT << "2addr: TO 3-ADDR: " << *New;
bool Sunk = false;
+
if (New->findRegisterUseOperand(regB, false, TRI))
// FIXME: Temporary workaround. If the new instruction doesn't
// uses regB, convertToThreeAddress must have created more
// then one instruction.
Sunk = Sink3AddrInstruction(mbbi, New, regB, mi);
- mbbi->erase(mi); // Nuke the old inst.
+
+ mbbi->erase(mi); // Nuke the old inst.
+
if (!Sunk) {
mi = New;
nmi = next(mi);
}
+
++NumConvertedTo3Addr;
- // Done with this instruction.
- break;
+ break; // Done with this instruction.
}
}
}
InstructionRearranged:
const TargetRegisterClass* rc = MF.getRegInfo().getRegClass(regA);
- TII->copyRegToReg(*mbbi, mi, regA, regB, rc, rc);
+ MachineInstr *Orig = MRI->getVRegDef(regB);
+ const TargetInstrDesc &OrigTID = Orig->getDesc();
+ bool SawStore = false;
+
+ if (EnableReMat && Orig && Orig->isSafeToMove(TII, SawStore) &&
+ OrigTID.isAsCheapAsAMove() && !OrigTID.mayLoad() &&
+ !OrigTID.isSimpleLoad()) {
+ DEBUG(cerr << "2addr: REMATTING : " << *Orig << "\n");
+ TII->reMaterialize(*mbbi, mi, regA, Orig);
+ ReMattedInstrs.insert(Orig);
+ } else {
+ TII->copyRegToReg(*mbbi, mi, regA, regB, rc, rc);
+ }
MachineBasicBlock::iterator prevMi = prior(mi);
DOUT << "\t\tprepend:\t"; DEBUG(prevMi->print(*cerr.stream(), &TM));
- // update live variables for regB
+ // Update live variables for regB.
LiveVariables::VarInfo& varInfoB = LV->getVarInfo(regB);
+
// regB is used in this BB.
varInfoB.UsedBlocks[mbbi->getNumber()] = true;
+
if (LV->removeVirtualRegisterKilled(regB, mbbi, mi))
LV->addVirtualRegisterKilled(regB, prevMi);
if (LV->removeVirtualRegisterDead(regB, mbbi, mi))
LV->addVirtualRegisterDead(regB, prevMi);
- // replace all occurences of regB with regA
+ // Replace all occurences of regB with regA.
for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
if (mi->getOperand(i).isRegister() &&
mi->getOperand(i).getReg() == regB)
DOUT << "\t\trewrite to:\t"; DEBUG(mi->print(*cerr.stream(), &TM));
}
+
mi = nmi;
}
}
+ if (EnableReMat) {
+ // Check to see if the instructions that we rematerialized are now dead. If
+ // they are, expunge them here.
+ SmallPtrSet<MachineInstr*, 8>::iterator I = ReMattedInstrs.begin();
+ SmallPtrSet<MachineInstr*, 8>::iterator E = ReMattedInstrs.end();
+
+ for (; I != E; ++I) {
+ MachineInstr *MI = *I;
+ bool InstrDead = true;
+
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = MI->getOperand(i);
+ if (!MO.isRegister())
+ continue;
+ unsigned MOReg = MO.getReg();
+
+ if (!MOReg || !MO.isDef() || (MO.isImplicit() && MO.isDead()))
+ continue;
+
+ if (MRI->use_begin(MOReg) != MRI->use_end()) {
+ InstrDead = false;
+ break;
+ }
+ }
+
+ if (InstrDead)
+ MI->eraseFromParent();
+ }
+ }
+
return MadeChange;
}
projects / oota-llvm.git / blobdiff