Make atomic load and store of pointers work. Tighten verification of atomic operations

[oota-llvm.git] / lib / CodeGen / TwoAddressInstructionPass.cpp

diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp
index d2f9a1b30dbde067e8fcfcadae79a08df892c822..aa601af21b0c21056938ab7de67cd91c3bd53e38 100644 (file)
--- a/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -235,7 +235,7 @@ bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB,
   // appropriate location, we can try to sink the current instruction
   // past it.
   if (!KillMI || KillMI->getParent() != MBB || KillMI == MI ||
-      KillMI->isTerminator())
+      KillMI == OldPos || KillMI->isTerminator())
     return false;
 
   // If any of the definitions are used by another instruction between the
@@ -278,6 +278,7 @@ bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB,
       }
     }
   }
+  assert(KillMO && "Didn't find kill");
 
   // Update kill and LV information.
   KillMO->setIsKill(false);
@@ -1209,27 +1210,28 @@ collectTiedOperands(MachineInstr *MI, TiedOperandMap &TiedOperands) {
     if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx))
       continue;
     AnyOps = true;
+    MachineOperand &SrcMO = MI->getOperand(SrcIdx);
+    MachineOperand &DstMO = MI->getOperand(DstIdx);
+    unsigned SrcReg = SrcMO.getReg();
+    unsigned DstReg = DstMO.getReg();
+    // Tied constraint already satisfied?
+    if (SrcReg == DstReg)
+      continue;
 
-    assert(MI->getOperand(SrcIdx).isReg() &&
-           MI->getOperand(SrcIdx).getReg() &&
-           MI->getOperand(SrcIdx).isUse() &&
-           "two address instruction invalid");
-
-    unsigned RegB = MI->getOperand(SrcIdx).getReg();
+    assert(SrcReg && SrcMO.isUse() && "two address instruction invalid");
 
     // Deal with <undef> uses immediately - simply rewrite the src operand.
-    if (MI->getOperand(SrcIdx).isUndef()) {
-      unsigned DstReg = MI->getOperand(DstIdx).getReg();
+    if (SrcMO.isUndef()) {
       // Constrain the DstReg register class if required.
       if (TargetRegisterInfo::isVirtualRegister(DstReg))
         if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx,
                                                              TRI, *MF))
           MRI->constrainRegClass(DstReg, RC);
-      MI->getOperand(SrcIdx).setReg(DstReg);
+      SrcMO.setReg(DstReg);
       DEBUG(dbgs() << "\t\trewrite undef:\t" << *MI);
       continue;
     }
-    TiedOperands[RegB].push_back(std::make_pair(SrcIdx, DstIdx));
+    TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx));
   }
   return AnyOps;
 }
@@ -1350,17 +1352,6 @@ TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI,
       }
     }
   }
-
-  // We didn't change anything if there was a single tied pair, and that
-  // pair didn't require copies.
-  if (AllUsesCopied || TiedPairs.size() > 1) {
-    // Schedule the source copy / remat inserted to form two-address
-    // instruction. FIXME: Does it matter the distance map may not be
-    // accurate after it's scheduled?
-    MachineBasicBlock::iterator PrevMI = MI;
-    --PrevMI;
-    TII->scheduleTwoAddrSource(PrevMI, MI, *TRI);
-  }
 }
 
 /// runOnMachineFunction - Reduce two-address instructions to two operands.
@@ -1387,9 +1378,6 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
   // This pass takes the function out of SSA form.
   MRI->leaveSSA();
 
-  // ReMatRegs - Keep track of the registers whose def's are remat'ed.
-  BitVector ReMatRegs(MRI->getNumVirtRegs());
-
   TiedOperandMap TiedOperands;
 
   SmallPtrSet<MachineInstr*, 8> Processed;
@@ -1478,15 +1466,6 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
     }
   }
 
-  // Some remat'ed instructions are dead.
-  for (int i = ReMatRegs.find_first(); i != -1; i = ReMatRegs.find_next(i)) {
-    unsigned VReg = TargetRegisterInfo::index2VirtReg(i);
-    if (MRI->use_nodbg_empty(VReg)) {
-      MachineInstr *DefMI = MRI->getVRegDef(VReg);
-      DefMI->eraseFromParent();
-    }
-  }
-
   // Eliminate REG_SEQUENCE instructions. Their whole purpose was to preseve
   // SSA form. It's now safe to de-SSA.
   MadeChange |= EliminateRegSequences();