//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file implements the VirtRegMap class.
//
-// It also contains implementations of the the Spiller interface, which, given a
+// It also contains implementations of the Spiller interface, which, given a
// virtual register map and a machine function, eliminates all virtual
// references by replacing them with physical register references - adding spill
// code as necessary.
//
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "spiller"
+#define DEBUG_TYPE "virtregmap"
#include "VirtRegMap.h"
#include "llvm/Function.h"
+#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/SSARegMap.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/DepthFirstIterator.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallSet.h"
#include <algorithm>
-#include <iostream>
using namespace llvm;
-namespace {
- Statistic<> NumSpills("spiller", "Number of register spills");
- Statistic<> NumStores("spiller", "Number of stores added");
- Statistic<> NumLoads ("spiller", "Number of loads added");
- Statistic<> NumReused("spiller", "Number of values reused");
- Statistic<> NumDSE ("spiller", "Number of dead stores elided");
-
- enum SpillerName { simple, local };
-
- cl::opt<SpillerName>
- SpillerOpt("spiller",
- cl::desc("Spiller to use: (default: local)"),
- cl::Prefix,
- cl::values(clEnumVal(simple, " simple spiller"),
- clEnumVal(local, " local spiller"),
- clEnumValEnd),
- cl::init(local));
-}
+STATISTIC(NumSpillSlots, "Number of spill slots allocated");
+STATISTIC(NumIdCopies, "Number of identity moves eliminated after rewriting");
//===----------------------------------------------------------------------===//
// VirtRegMap implementation
//===----------------------------------------------------------------------===//
+char VirtRegMap::ID = 0;
+
+INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false)
+
+bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
+ MRI = &mf.getRegInfo();
+ TII = mf.getTarget().getInstrInfo();
+ TRI = mf.getTarget().getRegisterInfo();
+ MF = &mf;
+
+ ReMatId = MAX_STACK_SLOT+1;
+ LowSpillSlot = HighSpillSlot = NO_STACK_SLOT;
+
+ Virt2PhysMap.clear();
+ Virt2StackSlotMap.clear();
+ Virt2ReMatIdMap.clear();
+ Virt2SplitMap.clear();
+ Virt2SplitKillMap.clear();
+ ReMatMap.clear();
+ ImplicitDefed.clear();
+ SpillSlotToUsesMap.clear();
+ MI2VirtMap.clear();
+ SpillPt2VirtMap.clear();
+ RestorePt2VirtMap.clear();
+ EmergencySpillMap.clear();
+ EmergencySpillSlots.clear();
+
+ SpillSlotToUsesMap.resize(8);
+ ImplicitDefed.resize(MF->getRegInfo().getNumVirtRegs());
+
+ allocatableRCRegs.clear();
+ for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
+ E = TRI->regclass_end(); I != E; ++I)
+ allocatableRCRegs.insert(std::make_pair(*I,
+ TRI->getAllocatableSet(mf, *I)));
+
+ grow();
+
+ return false;
+}
+
void VirtRegMap::grow() {
- Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg());
- Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg());
+ unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
+ Virt2PhysMap.resize(NumRegs);
+ Virt2StackSlotMap.resize(NumRegs);
+ Virt2ReMatIdMap.resize(NumRegs);
+ Virt2SplitMap.resize(NumRegs);
+ Virt2SplitKillMap.resize(NumRegs);
+ ReMatMap.resize(NumRegs);
+ ImplicitDefed.resize(NumRegs);
+}
+
+unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
+ int SS = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
+ RC->getAlignment());
+ if (LowSpillSlot == NO_STACK_SLOT)
+ LowSpillSlot = SS;
+ if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot)
+ HighSpillSlot = SS;
+ assert(SS >= LowSpillSlot && "Unexpected low spill slot");
+ unsigned Idx = SS-LowSpillSlot;
+ while (Idx >= SpillSlotToUsesMap.size())
+ SpillSlotToUsesMap.resize(SpillSlotToUsesMap.size()*2);
+ ++NumSpillSlots;
+ return SS;
+}
+
+unsigned VirtRegMap::getRegAllocPref(unsigned virtReg) {
+ std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(virtReg);
+ unsigned physReg = Hint.second;
+ if (TargetRegisterInfo::isVirtualRegister(physReg) && hasPhys(physReg))
+ physReg = getPhys(physReg);
+ if (Hint.first == 0)
+ return (TargetRegisterInfo::isPhysicalRegister(physReg))
+ ? physReg : 0;
+ return TRI->ResolveRegAllocHint(Hint.first, physReg, *MF);
}
int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
- assert(MRegisterInfo::isVirtualRegister(virtReg));
+ assert(TargetRegisterInfo::isVirtualRegister(virtReg));
assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
"attempt to assign stack slot to already spilled register");
- const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
- int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
- RC->getAlignment());
- Virt2StackSlotMap[virtReg] = frameIndex;
- ++NumSpills;
- return frameIndex;
+ const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
+ return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
}
-void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
- assert(MRegisterInfo::isVirtualRegister(virtReg));
+void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
+ assert(TargetRegisterInfo::isVirtualRegister(virtReg));
assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
"attempt to assign stack slot to already spilled register");
- Virt2StackSlotMap[virtReg] = frameIndex;
+ assert((SS >= 0 ||
+ (SS >= MF->getFrameInfo()->getObjectIndexBegin())) &&
+ "illegal fixed frame index");
+ Virt2StackSlotMap[virtReg] = SS;
+}
+
+int VirtRegMap::assignVirtReMatId(unsigned virtReg) {
+ assert(TargetRegisterInfo::isVirtualRegister(virtReg));
+ assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
+ "attempt to assign re-mat id to already spilled register");
+ Virt2ReMatIdMap[virtReg] = ReMatId;
+ return ReMatId++;
+}
+
+void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) {
+ assert(TargetRegisterInfo::isVirtualRegister(virtReg));
+ assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
+ "attempt to assign re-mat id to already spilled register");
+ Virt2ReMatIdMap[virtReg] = id;
+}
+
+int VirtRegMap::getEmergencySpillSlot(const TargetRegisterClass *RC) {
+ std::map<const TargetRegisterClass*, int>::iterator I =
+ EmergencySpillSlots.find(RC);
+ if (I != EmergencySpillSlots.end())
+ return I->second;
+ return EmergencySpillSlots[RC] = createSpillSlot(RC);
+}
+
+void VirtRegMap::addSpillSlotUse(int FI, MachineInstr *MI) {
+ if (!MF->getFrameInfo()->isFixedObjectIndex(FI)) {
+ // If FI < LowSpillSlot, this stack reference was produced by
+ // instruction selection and is not a spill
+ if (FI >= LowSpillSlot) {
+ assert(FI >= 0 && "Spill slot index should not be negative!");
+ assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size()
+ && "Invalid spill slot");
+ SpillSlotToUsesMap[FI-LowSpillSlot].insert(MI);
+ }
+ }
}
void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
- unsigned OpNo, MachineInstr *NewMI) {
+ MachineInstr *NewMI, ModRef MRInfo) {
// Move previous memory references folded to new instruction.
MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
MI2VirtMap.erase(I++);
}
- ModRef MRInfo;
- if (!OldMI->getOperand(OpNo).isDef()) {
- assert(OldMI->getOperand(OpNo).isUse() && "Operand is not use or def?");
- MRInfo = isRef;
- } else {
- MRInfo = OldMI->getOperand(OpNo).isUse() ? isModRef : isMod;
- }
-
// add new memory reference
MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
}
-void VirtRegMap::print(std::ostream &OS) const {
- const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
-
- OS << "********** REGISTER MAP **********\n";
- for (unsigned i = MRegisterInfo::FirstVirtualRegister,
- e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
- if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
- OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
-
- }
-
- for (unsigned i = MRegisterInfo::FirstVirtualRegister,
- e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
- if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
- OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
- OS << '\n';
-}
-
-void VirtRegMap::dump() const { print(std::cerr); }
-
-
-//===----------------------------------------------------------------------===//
-// Simple Spiller Implementation
-//===----------------------------------------------------------------------===//
-
-Spiller::~Spiller() {}
-
-namespace {
- struct SimpleSpiller : public Spiller {
- bool runOnMachineFunction(MachineFunction& mf, const VirtRegMap &VRM);
- };
-}
-
-bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF,
- const VirtRegMap &VRM) {
- DEBUG(std::cerr << "********** REWRITE MACHINE CODE **********\n");
- DEBUG(std::cerr << "********** Function: "
- << MF.getFunction()->getName() << '\n');
- const TargetMachine &TM = MF.getTarget();
- const MRegisterInfo &MRI = *TM.getRegisterInfo();
- bool *PhysRegsUsed = MF.getUsedPhysregs();
-
- // LoadedRegs - Keep track of which vregs are loaded, so that we only load
- // each vreg once (in the case where a spilled vreg is used by multiple
- // operands). This is always smaller than the number of operands to the
- // current machine instr, so it should be small.
- std::vector<unsigned> LoadedRegs;
-
- for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
- MBBI != E; ++MBBI) {
- DEBUG(std::cerr << MBBI->getBasicBlock()->getName() << ":\n");
- MachineBasicBlock &MBB = *MBBI;
- for (MachineBasicBlock::iterator MII = MBB.begin(),
- E = MBB.end(); MII != E; ++MII) {
- MachineInstr &MI = *MII;
- for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
- MachineOperand &MO = MI.getOperand(i);
- if (MO.isRegister() && MO.getReg())
- if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
- unsigned VirtReg = MO.getReg();
- unsigned PhysReg = VRM.getPhys(VirtReg);
- if (VRM.hasStackSlot(VirtReg)) {
- int StackSlot = VRM.getStackSlot(VirtReg);
- const TargetRegisterClass* RC =
- MF.getSSARegMap()->getRegClass(VirtReg);
-
- if (MO.isUse() &&
- std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
- == LoadedRegs.end()) {
- MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
- LoadedRegs.push_back(VirtReg);
- ++NumLoads;
- DEBUG(std::cerr << '\t' << *prior(MII));
- }
-
- if (MO.isDef()) {
- MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
- ++NumStores;
- }
- }
- PhysRegsUsed[PhysReg] = true;
- MI.SetMachineOperandReg(i, PhysReg);
- } else {
- PhysRegsUsed[MO.getReg()] = true;
- }
- }
-
- DEBUG(std::cerr << '\t' << MI);
- LoadedRegs.clear();
- }
- }
- return true;
-}
-
-//===----------------------------------------------------------------------===//
-// Local Spiller Implementation
-//===----------------------------------------------------------------------===//
-
-namespace {
- /// LocalSpiller - This spiller does a simple pass over the machine basic
- /// block to attempt to keep spills in registers as much as possible for
- /// blocks that have low register pressure (the vreg may be spilled due to
- /// register pressure in other blocks).
- class LocalSpiller : public Spiller {
- const MRegisterInfo *MRI;
- const TargetInstrInfo *TII;
- public:
- bool runOnMachineFunction(MachineFunction &MF, const VirtRegMap &VRM) {
- MRI = MF.getTarget().getRegisterInfo();
- TII = MF.getTarget().getInstrInfo();
- DEBUG(std::cerr << "\n**** Local spiller rewriting function '"
- << MF.getFunction()->getName() << "':\n");
-
- for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
- MBB != E; ++MBB)
- RewriteMBB(*MBB, VRM);
- return true;
- }
- private:
- void RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM);
- void ClobberPhysReg(unsigned PR, std::map<int, unsigned> &SpillSlots,
- std::multimap<unsigned, int> &PhysRegs);
- void ClobberPhysRegOnly(unsigned PR, std::map<int, unsigned> &SpillSlots,
- std::multimap<unsigned, int> &PhysRegs);
- void ModifyStackSlot(int Slot, std::map<int, unsigned> &SpillSlots,
- std::multimap<unsigned, int> &PhysRegs);
- };
+void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) {
+ MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(MI);
+ MI2VirtMap.insert(IP, std::make_pair(MI, std::make_pair(VirtReg, MRInfo)));
}
-void LocalSpiller::ClobberPhysRegOnly(unsigned PhysReg,
- std::map<int, unsigned> &SpillSlots,
- std::multimap<unsigned, int> &PhysRegsAvailable) {
- std::map<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(PhysReg);
- while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
- int Slot = I->second;
- PhysRegsAvailable.erase(I++);
- assert(SpillSlots[Slot] == PhysReg && "Bidirectional map mismatch!");
- SpillSlots.erase(Slot);
- DEBUG(std::cerr << "PhysReg " << MRI->getName(PhysReg)
- << " clobbered, invalidating SS#" << Slot << "\n");
-
+void VirtRegMap::RemoveMachineInstrFromMaps(MachineInstr *MI) {
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (!MO.isFI())
+ continue;
+ int FI = MO.getIndex();
+ if (MF->getFrameInfo()->isFixedObjectIndex(FI))
+ continue;
+ // This stack reference was produced by instruction selection and
+ // is not a spill
+ if (FI < LowSpillSlot)
+ continue;
+ assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size()
+ && "Invalid spill slot");
+ SpillSlotToUsesMap[FI-LowSpillSlot].erase(MI);
}
+ MI2VirtMap.erase(MI);
+ SpillPt2VirtMap.erase(MI);
+ RestorePt2VirtMap.erase(MI);
+ EmergencySpillMap.erase(MI);
}
-void LocalSpiller::ClobberPhysReg(unsigned PhysReg,
- std::map<int, unsigned> &SpillSlots,
- std::multimap<unsigned, int> &PhysRegsAvailable) {
- for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
- ClobberPhysRegOnly(*AS, SpillSlots, PhysRegsAvailable);
- ClobberPhysRegOnly(PhysReg, SpillSlots, PhysRegsAvailable);
-}
-
-/// ModifyStackSlot - This method is called when the value in a stack slot
-/// changes. This removes information about which register the previous value
-/// for this slot lives in (as the previous value is dead now).
-void LocalSpiller::ModifyStackSlot(int Slot, std::map<int,unsigned> &SpillSlots,
- std::multimap<unsigned, int> &PhysRegsAvailable) {
- std::map<int, unsigned>::iterator It = SpillSlots.find(Slot);
- if (It == SpillSlots.end()) return;
- unsigned Reg = It->second;
- SpillSlots.erase(It);
-
- // This register may hold the value of multiple stack slots, only remove this
- // stack slot from the set of values the register contains.
- std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
- for (; ; ++I) {
- assert(I != PhysRegsAvailable.end() && I->first == Reg &&
- "Map inverse broken!");
- if (I->second == Slot) break;
+/// FindUnusedRegisters - Gather a list of allocatable registers that
+/// have not been allocated to any virtual register.
+bool VirtRegMap::FindUnusedRegisters(LiveIntervals* LIs) {
+ unsigned NumRegs = TRI->getNumRegs();
+ UnusedRegs.reset();
+ UnusedRegs.resize(NumRegs);
+
+ BitVector Used(NumRegs);
+ for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
+ unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
+ if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG)
+ Used.set(Virt2PhysMap[Reg]);
}
- PhysRegsAvailable.erase(I);
-}
-
-
-// ReusedOp - For each reused operand, we keep track of a bit of information, in
-// case we need to rollback upon processing a new operand. See comments below.
-namespace {
- struct ReusedOp {
- // The MachineInstr operand that reused an available value.
- unsigned Operand;
-
- // StackSlot - The spill slot of the value being reused.
- unsigned StackSlot;
-
- // PhysRegReused - The physical register the value was available in.
- unsigned PhysRegReused;
-
- // AssignedPhysReg - The physreg that was assigned for use by the reload.
- unsigned AssignedPhysReg;
-
- // VirtReg - The virtual register itself.
- unsigned VirtReg;
-
- ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
- unsigned vreg)
- : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr),
- VirtReg(vreg) {}
- };
-}
-
-
-/// rewriteMBB - Keep track of which spills are available even after the
-/// register allocator is done with them. If possible, avoid reloading vregs.
-void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM) {
-
- // SpillSlotsAvailable - This map keeps track of all of the spilled virtual
- // register values that are still available, due to being loaded or stored to,
- // but not invalidated yet.
- std::map<int, unsigned> SpillSlotsAvailable;
-
- // PhysRegsAvailable - This is the inverse of SpillSlotsAvailable, indicating
- // which stack slot values are currently held by a physreg. This is used to
- // invalidate entries in SpillSlotsAvailable when a physreg is modified.
- std::multimap<unsigned, int> PhysRegsAvailable;
-
- DEBUG(std::cerr << MBB.getBasicBlock()->getName() << ":\n");
-
- std::vector<ReusedOp> ReusedOperands;
-
- // DefAndUseVReg - When we see a def&use operand that is spilled, keep track
- // of it. ".first" is the machine operand index (should always be 0 for now),
- // and ".second" is the virtual register that is spilled.
- std::vector<std::pair<unsigned, unsigned> > DefAndUseVReg;
-
- // MaybeDeadStores - When we need to write a value back into a stack slot,
- // keep track of the inserted store. If the stack slot value is never read
- // (because the value was used from some available register, for example), and
- // subsequently stored to, the original store is dead. This map keeps track
- // of inserted stores that are not used. If we see a subsequent store to the
- // same stack slot, the original store is deleted.
- std::map<int, MachineInstr*> MaybeDeadStores;
-
- bool *PhysRegsUsed = MBB.getParent()->getUsedPhysregs();
-
- for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
- MII != E; ) {
- MachineInstr &MI = *MII;
- MachineBasicBlock::iterator NextMII = MII; ++NextMII;
-
- ReusedOperands.clear();
- DefAndUseVReg.clear();
-
- // Process all of the spilled uses and all non spilled reg references.
- for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
- MachineOperand &MO = MI.getOperand(i);
- if (!MO.isRegister() || MO.getReg() == 0)
- continue; // Ignore non-register operands.
-
- if (MRegisterInfo::isPhysicalRegister(MO.getReg())) {
- // Ignore physregs for spilling, but remember that it is used by this
- // function.
- PhysRegsUsed[MO.getReg()] = true;
- continue;
- }
-
- assert(MRegisterInfo::isVirtualRegister(MO.getReg()) &&
- "Not a virtual or a physical register?");
-
- unsigned VirtReg = MO.getReg();
- if (!VRM.hasStackSlot(VirtReg)) {
- // This virtual register was assigned a physreg!
- unsigned Phys = VRM.getPhys(VirtReg);
- PhysRegsUsed[Phys] = true;
- MI.SetMachineOperandReg(i, Phys);
- continue;
- }
-
- // This virtual register is now known to be a spilled value.
- if (!MO.isUse())
- continue; // Handle defs in the loop below (handle use&def here though)
-
- // If this is both a def and a use, we need to emit a store to the
- // stack slot after the instruction. Keep track of D&U operands
- // because we are about to change it to a physreg here.
- if (MO.isDef()) {
- // Remember that this was a def-and-use operand, and that the
- // stack slot is live after this instruction executes.
- DefAndUseVReg.push_back(std::make_pair(i, VirtReg));
+ BitVector Allocatable = TRI->getAllocatableSet(*MF);
+ bool AnyUnused = false;
+ for (unsigned Reg = 1; Reg < NumRegs; ++Reg) {
+ if (Allocatable[Reg] && !Used[Reg] && !LIs->hasInterval(Reg)) {
+ bool ReallyUnused = true;
+ for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
+ if (Used[*AS] || LIs->hasInterval(*AS)) {
+ ReallyUnused = false;
+ break;
+ }
}
-
- int StackSlot = VRM.getStackSlot(VirtReg);
- unsigned PhysReg;
-
- // Check to see if this stack slot is available.
- std::map<int, unsigned>::iterator SSI =
- SpillSlotsAvailable.find(StackSlot);
- if (SSI != SpillSlotsAvailable.end()) {
- DEBUG(std::cerr << "Reusing SS#" << StackSlot << " from physreg "
- << MRI->getName(SSI->second) << " for vreg"
- << VirtReg <<" instead of reloading into physreg "
- << MRI->getName(VRM.getPhys(VirtReg)) << "\n");
- // If this stack slot value is already available, reuse it!
- PhysReg = SSI->second;
- MI.SetMachineOperandReg(i, PhysReg);
-
- // The only technical detail we have is that we don't know that
- // PhysReg won't be clobbered by a reloaded stack slot that occurs
- // later in the instruction. In particular, consider 'op V1, V2'.
- // If V1 is available in physreg R0, we would choose to reuse it
- // here, instead of reloading it into the register the allocator
- // indicated (say R1). However, V2 might have to be reloaded
- // later, and it might indicate that it needs to live in R0. When
- // this occurs, we need to have information available that
- // indicates it is safe to use R1 for the reload instead of R0.
- //
- // To further complicate matters, we might conflict with an alias,
- // or R0 and R1 might not be compatible with each other. In this
- // case, we actually insert a reload for V1 in R1, ensuring that
- // we can get at R0 or its alias.
- ReusedOperands.push_back(ReusedOp(i, StackSlot, PhysReg,
- VRM.getPhys(VirtReg), VirtReg));
- ++NumReused;
- continue;
+ if (ReallyUnused) {
+ AnyUnused = true;
+ UnusedRegs.set(Reg);
}
-
- // Otherwise, reload it and remember that we have it.
- PhysReg = VRM.getPhys(VirtReg);
- assert(PhysReg && "Must map virtreg to physreg!");
- const TargetRegisterClass* RC =
- MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
-
- RecheckRegister:
- // Note that, if we reused a register for a previous operand, the
- // register we want to reload into might not actually be
- // available. If this occurs, use the register indicated by the
- // reuser.
- if (!ReusedOperands.empty()) // This is most often empty.
- for (unsigned ro = 0, e = ReusedOperands.size(); ro != e; ++ro)
- if (ReusedOperands[ro].PhysRegReused == PhysReg) {
- // Yup, use the reload register that we didn't use before.
- PhysReg = ReusedOperands[ro].AssignedPhysReg;
- goto RecheckRegister;
- } else {
- ReusedOp &Op = ReusedOperands[ro];
- unsigned PRRU = Op.PhysRegReused;
- if (MRI->areAliases(PRRU, PhysReg)) {
- // Okay, we found out that an alias of a reused register
- // was used. This isn't good because it means we have
- // to undo a previous reuse.
- const TargetRegisterClass *AliasRC =
- MBB.getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
- MRI->loadRegFromStackSlot(MBB, &MI, Op.AssignedPhysReg,
- Op.StackSlot, AliasRC);
- ClobberPhysReg(Op.AssignedPhysReg, SpillSlotsAvailable,
- PhysRegsAvailable);
-
- // Any stores to this stack slot are not dead anymore.
- MaybeDeadStores.erase(Op.StackSlot);
-
- MI.SetMachineOperandReg(Op.Operand, Op.AssignedPhysReg);
- PhysRegsAvailable.insert(std::make_pair(Op.AssignedPhysReg,
- Op.StackSlot));
- SpillSlotsAvailable[Op.StackSlot] = Op.AssignedPhysReg;
- PhysRegsAvailable.erase(Op.PhysRegReused);
- DEBUG(std::cerr << "Remembering SS#" << Op.StackSlot
- << " in physreg "
- << MRI->getName(Op.AssignedPhysReg) << "\n");
- ++NumLoads;
- DEBUG(std::cerr << '\t' << *prior(MII));
-
- DEBUG(std::cerr << "Reuse undone!\n");
- ReusedOperands.erase(ReusedOperands.begin()+ro);
- --NumReused;
- goto ContinueReload;
- }
- }
- ContinueReload:
- PhysRegsUsed[PhysReg] = true;
- MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
- // This invalidates PhysReg.
- ClobberPhysReg(PhysReg, SpillSlotsAvailable, PhysRegsAvailable);
-
- // Any stores to this stack slot are not dead anymore.
- MaybeDeadStores.erase(StackSlot);
-
- MI.SetMachineOperandReg(i, PhysReg);
- PhysRegsAvailable.insert(std::make_pair(PhysReg, StackSlot));
- SpillSlotsAvailable[StackSlot] = PhysReg;
- DEBUG(std::cerr << "Remembering SS#" << StackSlot <<" in physreg "
- << MRI->getName(PhysReg) << "\n");
- ++NumLoads;
- DEBUG(std::cerr << '\t' << *prior(MII));
}
+ }
- // Loop over all of the implicit defs, clearing them from our available
- // sets.
- for (const unsigned *ImpDef = TII->getImplicitDefs(MI.getOpcode());
- *ImpDef; ++ImpDef) {
- PhysRegsUsed[*ImpDef] = true;
- ClobberPhysReg(*ImpDef, SpillSlotsAvailable, PhysRegsAvailable);
- }
+ return AnyUnused;
+}
- DEBUG(std::cerr << '\t' << MI);
-
- // If we have folded references to memory operands, make sure we clear all
- // physical registers that may contain the value of the spilled virtual
- // register
- VirtRegMap::MI2VirtMapTy::const_iterator I, End;
- for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
- DEBUG(std::cerr << "Folded vreg: " << I->second.first << " MR: "
- << I->second.second);
- unsigned VirtReg = I->second.first;
- VirtRegMap::ModRef MR = I->second.second;
- if (!VRM.hasStackSlot(VirtReg)) {
- DEBUG(std::cerr << ": No stack slot!\n");
- continue;
- }
- int SS = VRM.getStackSlot(VirtReg);
- DEBUG(std::cerr << " - StackSlot: " << SS << "\n");
-
- // If this folded instruction is just a use, check to see if it's a
- // straight load from the virt reg slot.
- if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
- int FrameIdx;
- if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
- // If this spill slot is available, turn it into a copy (or nothing)
- // instead of leaving it as a load!
- std::map<int, unsigned>::iterator It = SpillSlotsAvailable.find(SS);
- if (FrameIdx == SS && It != SpillSlotsAvailable.end()) {
- DEBUG(std::cerr << "Promoted Load To Copy: " << MI);
- MachineFunction &MF = *MBB.getParent();
- if (DestReg != It->second) {
- MRI->copyRegToReg(MBB, &MI, DestReg, It->second,
- MF.getSSARegMap()->getRegClass(VirtReg));
- // Revisit the copy so we make sure to notice the effects of the
- // operation on the destreg (either needing to RA it if it's
- // virtual or needing to clobber any values if it's physical).
- NextMII = &MI;
- --NextMII; // backtrack to the copy.
- }
- MBB.erase(&MI);
- goto ProcessNextInst;
+void VirtRegMap::rewrite(SlotIndexes *Indexes) {
+ DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
+ << "********** Function: "
+ << MF->getFunction()->getName() << '\n');
+ DEBUG(dump());
+ SmallVector<unsigned, 8> SuperDeads;
+ SmallVector<unsigned, 8> SuperDefs;
+ SmallVector<unsigned, 8> SuperKills;
+
+ for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
+ MBBI != MBBE; ++MBBI) {
+ DEBUG(MBBI->print(dbgs(), Indexes));
+ for (MachineBasicBlock::iterator MII = MBBI->begin(), MIE = MBBI->end();
+ MII != MIE;) {
+ MachineInstr *MI = MII;
+ ++MII;
+
+ for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
+ MOE = MI->operands_end(); MOI != MOE; ++MOI) {
+ MachineOperand &MO = *MOI;
+ if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
+ continue;
+ unsigned VirtReg = MO.getReg();
+ unsigned PhysReg = getPhys(VirtReg);
+ assert(PhysReg != NO_PHYS_REG && "Instruction uses unmapped VirtReg");
+
+ // Preserve semantics of sub-register operands.
+ if (MO.getSubReg()) {
+ // A virtual register kill refers to the whole register, so we may
+ // have to add <imp-use,kill> operands for the super-register. A
+ // partial redef always kills and redefines the super-register.
+ if (MO.readsReg() && (MO.isDef() || MO.isKill()))
+ SuperKills.push_back(PhysReg);
+
+ if (MO.isDef()) {
+ // The <def,undef> flag only makes sense for sub-register defs, and
+ // we are substituting a full physreg. An <imp-use,kill> operand
+ // from the SuperKills list will represent the partial read of the
+ // super-register.
+ MO.setIsUndef(false);
+
+ // Also add implicit defs for the super-register.
+ if (MO.isDead())
+ SuperDeads.push_back(PhysReg);
+ else
+ SuperDefs.push_back(PhysReg);
}
- }
- }
- // If this reference is not a use, any previous store is now dead.
- // Otherwise, the store to this stack slot is not dead anymore.
- std::map<int, MachineInstr*>::iterator MDSI = MaybeDeadStores.find(SS);
- if (MDSI != MaybeDeadStores.end()) {
- if (MR & VirtRegMap::isRef) // Previous store is not dead.
- MaybeDeadStores.erase(MDSI);
- else {
- // If we get here, the store is dead, nuke it now.
- assert(MR == VirtRegMap::isMod && "Can't be modref!");
- MBB.erase(MDSI->second);
- MaybeDeadStores.erase(MDSI);
- ++NumDSE;
+ // PhysReg operands cannot have subregister indexes.
+ PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg());
+ assert(PhysReg && "Invalid SubReg for physical register");
+ MO.setSubReg(0);
}
+ // Rewrite. Note we could have used MachineOperand::substPhysReg(), but
+ // we need the inlining here.
+ MO.setReg(PhysReg);
}
- // If the spill slot value is available, and this is a new definition of
- // the value, the value is not available anymore.
- if (MR & VirtRegMap::isMod) {
- // Notice that the value in this stack slot has been modified.
- ModifyStackSlot(SS, SpillSlotsAvailable, PhysRegsAvailable);
-
- // If this is *just* a mod of the value, check to see if this is just a
- // store to the spill slot (i.e. the spill got merged into the copy). If
- // so, realize that the vreg is available now, and add the store to the
- // MaybeDeadStore info.
- int StackSlot;
- if (!(MR & VirtRegMap::isRef)) {
- if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
- assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
- "Src hasn't been allocated yet?");
- // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
- // this as a potentially dead store in case there is a subsequent
- // store into the stack slot without a read from it.
- MaybeDeadStores[StackSlot] = &MI;
-
- // If the stack slot value was previously available in some other
- // register, change it now. Otherwise, make the register available,
- // in PhysReg.
- SpillSlotsAvailable[StackSlot] = SrcReg;
- PhysRegsAvailable.insert(std::make_pair(SrcReg, StackSlot));
- DEBUG(std::cerr << "Updating SS#" << StackSlot << " in physreg "
- << MRI->getName(SrcReg) << " for virtreg #"
- << VirtReg << "\n" << MI);
- }
+ // Add any missing super-register kills after rewriting the whole
+ // instruction.
+ while (!SuperKills.empty())
+ MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
+
+ while (!SuperDeads.empty())
+ MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
+
+ while (!SuperDefs.empty())
+ MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI);
+
+ DEBUG(dbgs() << "> " << *MI);
+
+ // Finally, remove any identity copies.
+ if (MI->isIdentityCopy()) {
+ ++NumIdCopies;
+ if (MI->getNumOperands() == 2) {
+ DEBUG(dbgs() << "Deleting identity copy.\n");
+ RemoveMachineInstrFromMaps(MI);
+ if (Indexes)
+ Indexes->removeMachineInstrFromMaps(MI);
+ // It's safe to erase MI because MII has already been incremented.
+ MI->eraseFromParent();
+ } else {
+ // Transform identity copy to a KILL to deal with subregisters.
+ MI->setDesc(TII->get(TargetOpcode::KILL));
+ DEBUG(dbgs() << "Identity copy: " << *MI);
}
}
}
+ }
- // Process all of the spilled defs.
- for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
- MachineOperand &MO = MI.getOperand(i);
- if (MO.isRegister() && MO.getReg() && MO.isDef()) {
- unsigned VirtReg = MO.getReg();
+ // Tell MRI about physical registers in use.
+ for (unsigned Reg = 1, RegE = TRI->getNumRegs(); Reg != RegE; ++Reg)
+ if (!MRI->reg_nodbg_empty(Reg))
+ MRI->setPhysRegUsed(Reg);
+}
- bool TakenCareOf = false;
- if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
- // Check to see if this is a def-and-use vreg operand that we do need
- // to insert a store for.
- bool OpTakenCareOf = false;
- if (MO.isUse() && !DefAndUseVReg.empty()) {
- for (unsigned dau = 0, e = DefAndUseVReg.size(); dau != e; ++dau)
- if (DefAndUseVReg[dau].first == i) {
- VirtReg = DefAndUseVReg[dau].second;
- OpTakenCareOf = true;
- break;
- }
- }
+void VirtRegMap::print(raw_ostream &OS, const Module* M) const {
+ const TargetRegisterInfo* TRI = MF->getTarget().getRegisterInfo();
+ const MachineRegisterInfo &MRI = MF->getRegInfo();
- if (!OpTakenCareOf) {
- ClobberPhysReg(VirtReg, SpillSlotsAvailable, PhysRegsAvailable);
- TakenCareOf = true;
- }
- }
+ OS << "********** REGISTER MAP **********\n";
+ for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
+ unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
+ if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
+ OS << '[' << PrintReg(Reg, TRI) << " -> "
+ << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
+ << MRI.getRegClass(Reg)->getName() << "\n";
+ }
+ }
- if (!TakenCareOf) {
- // The only vregs left are stack slot definitions.
- int StackSlot = VRM.getStackSlot(VirtReg);
- const TargetRegisterClass *RC =
- MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
- unsigned PhysReg;
-
- // If this is a def&use operand, and we used a different physreg for
- // it than the one assigned, make sure to execute the store from the
- // correct physical register.
- if (MO.getReg() == VirtReg)
- PhysReg = VRM.getPhys(VirtReg);
- else
- PhysReg = MO.getReg();
-
- PhysRegsUsed[PhysReg] = true;
- MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
- DEBUG(std::cerr << "Store:\t" << *next(MII));
- MI.SetMachineOperandReg(i, PhysReg);
-
- // If there is a dead store to this stack slot, nuke it now.
- MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
- if (LastStore) {
- DEBUG(std::cerr << " Killed store:\t" << *LastStore);
- ++NumDSE;
- MBB.erase(LastStore);
- }
- LastStore = next(MII);
-
- // If the stack slot value was previously available in some other
- // register, change it now. Otherwise, make the register available,
- // in PhysReg.
- ModifyStackSlot(StackSlot, SpillSlotsAvailable, PhysRegsAvailable);
- ClobberPhysReg(PhysReg, SpillSlotsAvailable, PhysRegsAvailable);
-
- PhysRegsAvailable.insert(std::make_pair(PhysReg, StackSlot));
- SpillSlotsAvailable[StackSlot] = PhysReg;
- DEBUG(std::cerr << "Updating SS#" << StackSlot <<" in physreg "
- << MRI->getName(PhysReg) << " for virtreg #"
- << VirtReg << "\n");
-
- ++NumStores;
- VirtReg = PhysReg;
- }
- }
+ for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
+ unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
+ if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
+ OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
+ << "] " << MRI.getRegClass(Reg)->getName() << "\n";
}
- ProcessNextInst:
- MII = NextMII;
}
+ OS << '\n';
}
-
-
-llvm::Spiller* llvm::createSpiller() {
- switch (SpillerOpt) {
- default: assert(0 && "Unreachable!");
- case local:
- return new LocalSpiller();
- case simple:
- return new SimpleSpiller();
- }
+void VirtRegMap::dump() const {
+ print(dbgs());
}
projects / oota-llvm.git / blobdiff