Use live out sets for return values instead of imp_defs, which is cleaner and faster.

[oota-llvm.git] / lib / CodeGen / VirtRegMap.cpp

diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index c72c18a94c00d8435a50684766b8fed506c95b30..b9925e2b20df083be6ae9392a73b2424c873eaac 100644 (file)
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -133,13 +133,14 @@ namespace {
   };
 }
 
-bool SimpleSpiller::runOnMachineFunction(MachineFunction& MF,
-                                         const VirtRegMap& VRM) {
+bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF,
+                                         const VirtRegMap &VRM) {
   DEBUG(std::cerr << "********** REWRITE MACHINE CODE **********\n");
   DEBUG(std::cerr << "********** Function: "
                   << MF.getFunction()->getName() << '\n');
-  const TargetMachine& TM = MF.getTarget();
-  const MRegisterInfo& MRI = *TM.getRegisterInfo();
+  const TargetMachine &TM = MF.getTarget();
+  const MRegisterInfo &MRI = *TM.getRegisterInfo();
+  bool *PhysRegsUsed = MF.getUsedPhysregs();
 
   // LoadedRegs - Keep track of which vregs are loaded, so that we only load
   // each vreg once (in the case where a spilled vreg is used by multiple
@@ -156,30 +157,34 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction& MF,
       MachineInstr &MI = *MII;
       for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
         MachineOperand &MO = MI.getOperand(i);
-        if (MO.isRegister() && MO.getReg() &&
-            MRegisterInfo::isVirtualRegister(MO.getReg())) {
-          unsigned VirtReg = MO.getReg();
-          unsigned PhysReg = VRM.getPhys(VirtReg);
-          if (VRM.hasStackSlot(VirtReg)) {
-            int StackSlot = VRM.getStackSlot(VirtReg);
-
-            if (MO.isUse() &&
-                std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
-                           == LoadedRegs.end()) {
-              MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot);
-              LoadedRegs.push_back(VirtReg);
-              ++NumLoads;
-              DEBUG(std::cerr << '\t' << *prior(MII));
-            }
-
-            if (MO.isDef()) {
-              MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot);
-              ++NumStores;
+        if (MO.isRegister() && MO.getReg())
+          if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
+            unsigned VirtReg = MO.getReg();
+            unsigned PhysReg = VRM.getPhys(VirtReg);
+            if (VRM.hasStackSlot(VirtReg)) {
+              int StackSlot = VRM.getStackSlot(VirtReg);
+              
+              if (MO.isUse() &&
+                  std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
+                  == LoadedRegs.end()) {
+                MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot);
+                LoadedRegs.push_back(VirtReg);
+                ++NumLoads;
+                DEBUG(std::cerr << '\t' << *prior(MII));
+              }
+              
+              if (MO.isDef()) {
+                MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot);
+                ++NumStores;
+              }
             }
+            PhysRegsUsed[PhysReg] = true;
+            MI.SetMachineOperandReg(i, PhysReg);
+          } else {
+            PhysRegsUsed[MO.getReg()] = true;
           }
-          MI.SetMachineOperandReg(i, PhysReg);
-        }
       }
+
       DEBUG(std::cerr << '\t' << MI);
       LoadedRegs.clear();
     }
@@ -296,6 +301,8 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM) {
   // same stack slot, the original store is deleted.
   std::map<int, MachineInstr*> MaybeDeadStores;
 
+  bool *PhysRegsUsed = MBB.getParent()->getUsedPhysregs();
+
   for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
        MII != E; ) {
     MachineInstr &MI = *MII;
@@ -308,12 +315,17 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM) {
     for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
       MachineOperand &MO = MI.getOperand(i);
       if (MO.isRegister() && MO.getReg() &&
-          MRegisterInfo::isVirtualRegister(MO.getReg())) {
+          MRegisterInfo::isPhysicalRegister(MO.getReg()))
+        PhysRegsUsed[MO.getReg()] = true;
+      else if (MO.isRegister() && MO.getReg() &&
+               MRegisterInfo::isVirtualRegister(MO.getReg())) {
         unsigned VirtReg = MO.getReg();
 
         if (!VRM.hasStackSlot(VirtReg)) {
           // This virtual register was assigned a physreg!
-          MI.SetMachineOperandReg(i, VRM.getPhys(VirtReg));
+          unsigned Phys = VRM.getPhys(VirtReg);
+          PhysRegsUsed[Phys] = true;
+          MI.SetMachineOperandReg(i, Phys);
         } else {
           // Is this virtual register a spilled value?
           if (MO.isUse()) {
@@ -397,7 +409,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM) {
                       }
                   }
             ContinueReload:
-
+              PhysRegsUsed[PhysReg] = true;
               MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot);
               // This invalidates PhysReg.
               ClobberPhysReg(PhysReg, SpillSlotsAvailable, PhysRegsAvailable);
@@ -429,9 +441,11 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM) {
 
     // Loop over all of the implicit defs, clearing them from our available
     // sets.
-    const TargetInstrDescriptor &InstrDesc = TII->get(MI.getOpcode());
-    for (const unsigned* ImpDef = InstrDesc.ImplicitDefs; *ImpDef; ++ImpDef)
+    for (const unsigned *ImpDef = TII->getImplicitDefs(MI.getOpcode());
+         *ImpDef; ++ImpDef) {
+      PhysRegsUsed[*ImpDef] = true;
       ClobberPhysReg(*ImpDef, SpillSlotsAvailable, PhysRegsAvailable);
+    }
 
     DEBUG(std::cerr << '\t' << MI);
 
@@ -516,6 +530,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM) {
           else
             PhysReg = MO.getReg();
 
+          PhysRegsUsed[PhysReg] = true;
           MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot);
           DEBUG(std::cerr << "Store:\t" << *next(MII));
           MI.SetMachineOperandReg(i, PhysReg);