Reorder methods alphabetically. No functionality change.

[oota-llvm.git] / lib / CodeGen / VirtRegMap.h

diff --git a/lib/CodeGen/VirtRegMap.h b/lib/CodeGen/VirtRegMap.h
index 7ebf31eeff37aacbb8bf3bdf2a643e1cd0c03fa5..52c4486392e058c8b2c5eb0fb2a292edf80ffd33 100644 (file)
--- a/lib/CodeGen/VirtRegMap.h
+++ b/lib/CodeGen/VirtRegMap.h
@@ -18,7 +18,7 @@
 #define LLVM_CODEGEN_VIRTREGMAP_H
 
 #include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/IndexedMap.h"
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/Support/Streams.h"
@@ -58,7 +58,7 @@ namespace llvm {
     /// at.
     IndexedMap<int, VirtReg2IndexFunctor> Virt2StackSlotMap;
 
-    /// Virt2StackSlotMap - This is virtual register to rematerialization id
+    /// Virt2ReMatIdMap - This is virtual register to rematerialization id
     /// mapping. Each spilled virtual register that should be remat'd has an
     /// entry in it which corresponds to the remat id.
     IndexedMap<int, VirtReg2IndexFunctor> Virt2ReMatIdMap;
@@ -116,6 +116,10 @@ namespace llvm {
     /// SpillSlotToUsesMap - Records uses for each register spill slot.
     SmallVector<SmallPtrSet<MachineInstr*, 4>, 8> SpillSlotToUsesMap;
 
+    /// ImplicitDefed - One bit for each virtual register. If set it indicates
+    /// the register is implicitly defined.
+    BitVector ImplicitDefed;
+
     VirtRegMap(const VirtRegMap&);     // DO NOT IMPLEMENT
     void operator=(const VirtRegMap&); // DO NOT IMPLEMENT
 
@@ -173,7 +177,7 @@ namespace llvm {
       return Virt2SplitMap[virtReg];
     }
 
-    /// @brief returns true is the specified virtual register is not
+    /// @brief returns true if the specified virtual register is not
     /// mapped to a stack slot or rematerialized.
     bool isAssignedReg(unsigned virtReg) const {
       if (getStackSlot(virtReg) == NO_STACK_SLOT &&
@@ -268,6 +272,8 @@ namespace llvm {
       }
     }
 
+    /// @brief - transfer spill point information from one instruction to
+    /// another.
     void transferSpillPts(MachineInstr *Old, MachineInstr *New) {
       std::map<MachineInstr*,std::vector<std::pair<unsigned,bool> > >::iterator
         I = SpillPt2VirtMap.find(Old);
@@ -343,6 +349,21 @@ namespace llvm {
       return EmergencySpillMap[MI];
     }
 
+    /// @brief - transfer emergency spill information from one instruction to
+    /// another.
+    void transferEmergencySpills(MachineInstr *Old, MachineInstr *New) {
+      std::map<MachineInstr*,std::vector<unsigned> >::iterator I =
+        EmergencySpillMap.find(Old);
+      if (I == EmergencySpillMap.end())
+        return;
+      while (!I->second.empty()) {
+        unsigned virtReg = I->second.back();
+        I->second.pop_back();
+        addEmergencySpill(virtReg, New);
+      }
+      EmergencySpillMap.erase(I);
+    }
+
     /// @brief return or get a emergency spill slot for the register class.
     int getEmergencySpillSlot(const TargetRegisterClass *RC);
 
@@ -365,6 +386,16 @@ namespace llvm {
       return !SpillSlotToUsesMap[FrameIndex-LowSpillSlot].empty();
     }
 
+    /// @brief Mark the specified register as being implicitly defined.
+    void setIsImplicitlyDefined(unsigned VirtReg) {
+      ImplicitDefed.set(VirtReg-TargetRegisterInfo::FirstVirtualRegister);
+    }
+
+    /// @brief Returns true if the virtual register is implicitly defined.
+    bool isImplicitlyDefined(unsigned VirtReg) const {
+      return ImplicitDefed[VirtReg-TargetRegisterInfo::FirstVirtualRegister];
+    }
+
     /// @brief Updates information about the specified virtual register's value
     /// folded into newMI machine instruction.
     void virtFolded(unsigned VirtReg, MachineInstr *OldMI, MachineInstr *NewMI,