[X86][Haswell][SchedModel] Add architecture specific scheduling models.

[oota-llvm.git] / lib / DebugInfo / DWARFAbbreviationDeclaration.h

diff --git a/lib/DebugInfo/DWARFAbbreviationDeclaration.h b/lib/DebugInfo/DWARFAbbreviationDeclaration.h
index e9b072eb86d8e497e609d236a9fc1eb54010a946..bb05c302be9a6d2f20dd0297cf9d6cea7c1ba910 100644 (file)
--- a/lib/DebugInfo/DWARFAbbreviationDeclaration.h
+++ b/lib/DebugInfo/DWARFAbbreviationDeclaration.h
@@ -7,8 +7,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_DEBUGINFO_DWARFABBREVIATIONDECLARATION_H
-#define LLVM_DEBUGINFO_DWARFABBREVIATIONDECLARATION_H
+#ifndef LLVM_LIB_DEBUGINFO_DWARFABBREVIATIONDECLARATION_H
+#define LLVM_LIB_DEBUGINFO_DWARFABBREVIATIONDECLARATION_H
 
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/DataExtractor.h"
@@ -27,19 +27,24 @@ class DWARFAbbreviationDeclaration {
     uint16_t Attr;
     uint16_t Form;
   };
-  SmallVector<AttributeSpec, 8> Attributes;
+  typedef SmallVector<AttributeSpec, 8> AttributeSpecVector;
+  AttributeSpecVector AttributeSpecs;
 public:
   DWARFAbbreviationDeclaration();
 
   uint32_t getCode() const { return Code; }
   uint32_t getTag() const { return Tag; }
   bool hasChildren() const { return HasChildren; }
-  uint32_t getNumAttributes() const { return Attributes.size(); }
-  uint16_t getAttrByIndex(uint32_t idx) const {
-    return idx < Attributes.size() ? Attributes[idx].Attr : 0;
+
+  typedef iterator_range<AttributeSpecVector::const_iterator>
+  attr_iterator_range;
+
+  attr_iterator_range attributes() const {
+    return attr_iterator_range(AttributeSpecs.begin(), AttributeSpecs.end());
   }
+
   uint16_t getFormByIndex(uint32_t idx) const {
-    return idx < Attributes.size() ? Attributes[idx].Form : 0;
+    return idx < AttributeSpecs.size() ? AttributeSpecs[idx].Form : 0;
   }
 
   uint32_t findAttributeIndex(uint16_t attr) const;