Fix a nasty bug in DAGCombine of STORE nodes.

[oota-llvm.git] / lib / MC / MCDisassembler / Disassembler.h

diff --git a/lib/MC/MCDisassembler/Disassembler.h b/lib/MC/MCDisassembler/Disassembler.h
index 880a31ad76b91b81d5557d7d1abd97f8908487aa..46d0c4c3d94c0879f6e66fa22dcdca73ad285fc6 100644 (file)
--- a/lib/MC/MCDisassembler/Disassembler.h
+++ b/lib/MC/MCDisassembler/Disassembler.h
@@ -14,14 +14,13 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_MC_DISASSEMBLER_H
-#define LLVM_MC_DISASSEMBLER_H
+#ifndef LLVM_LIB_MC_MCDISASSEMBLER_DISASSEMBLER_H
+#define LLVM_LIB_MC_MCDISASSEMBLER_DISASSEMBLER_H
 
 #include "llvm-c/Disassembler.h"
-#include <string>
-#include "llvm/ADT/OwningPtr.h"
 #include "llvm/ADT/SmallString.h"
 #include "llvm/Support/raw_ostream.h"
+#include <string>
 
 namespace llvm {
 class MCContext;
@@ -56,23 +55,27 @@ private:
   // LLVMDisasmInstruction().
   //
   // The LLVM target corresponding to the disassembler.
-  // FIXME: using llvm::OwningPtr<const llvm::Target> causes a malloc error
+  // FIXME: using std::unique_ptr<const llvm::Target> causes a malloc error
   //        when this LLVMDisasmContext is deleted.
   const Target *TheTarget;
   // The assembly information for the target architecture.
-  llvm::OwningPtr<const llvm::MCAsmInfo> MAI;
+  std::unique_ptr<const llvm::MCAsmInfo> MAI;
   // The register information for the target architecture.
-  llvm::OwningPtr<const llvm::MCRegisterInfo> MRI;
+  std::unique_ptr<const llvm::MCRegisterInfo> MRI;
   // The subtarget information for the target architecture.
-  llvm::OwningPtr<const llvm::MCSubtargetInfo> MSI;
+  std::unique_ptr<const llvm::MCSubtargetInfo> MSI;
   // The instruction information for the target architecture.
-  llvm::OwningPtr<const llvm::MCInstrInfo> MII;
+  std::unique_ptr<const llvm::MCInstrInfo> MII;
   // The assembly context for creating symbols and MCExprs.
-  llvm::OwningPtr<const llvm::MCContext> Ctx;
+  std::unique_ptr<const llvm::MCContext> Ctx;
   // The disassembler for the target architecture.
-  llvm::OwningPtr<const llvm::MCDisassembler> DisAsm;
+  std::unique_ptr<const llvm::MCDisassembler> DisAsm;
   // The instruction printer for the target architecture.
-  llvm::OwningPtr<llvm::MCInstPrinter> IP;
+  std::unique_ptr<llvm::MCInstPrinter> IP;
+  // The options used to set up the disassembler.
+  uint64_t Options;
+  // The CPU string.
+  std::string CPU;
 
 public:
   // Comment stream and backing vector.
@@ -90,6 +93,7 @@ public:
                     MCInstPrinter *iP) : TripleName(tripleName),
                     DisInfo(disInfo), TagType(tagType), GetOpInfo(getOpInfo),
                     SymbolLookUp(symbolLookUp), TheTarget(theTarget),
+                    Options(0),
                     CommentStream(CommentsToEmit) {
     MAI.reset(mAI);
     MRI.reset(mRI);
@@ -99,9 +103,25 @@ public:
     DisAsm.reset(disAsm);
     IP.reset(iP);
   }
+  const std::string &getTripleName() const { return TripleName; }
+  void *getDisInfo() const { return DisInfo; }
+  int getTagType() const { return TagType; }
+  LLVMOpInfoCallback getGetOpInfo() const { return GetOpInfo; }
+  LLVMSymbolLookupCallback getSymbolLookupCallback() const {
+    return SymbolLookUp;
+  }
+  const Target *getTarget() const { return TheTarget; }
   const MCDisassembler *getDisAsm() const { return DisAsm.get(); }
   const MCAsmInfo *getAsmInfo() const { return MAI.get(); }
+  const MCInstrInfo *getInstrInfo() const { return MII.get(); }
+  const MCRegisterInfo *getRegisterInfo() const { return MRI.get(); }
+  const MCSubtargetInfo *getSubtargetInfo() const { return MSI.get(); }
   MCInstPrinter *getIP() { return IP.get(); }
+  void setIP(MCInstPrinter *NewIP) { IP.reset(NewIP); }
+  uint64_t getOptions() const { return Options; }
+  void addOptions(uint64_t Options) { this->Options |= Options; }
+  StringRef getCPU() const { return CPU; }
+  void setCPU(const char *CPU) { this->CPU = CPU; }
 };
 
 } // namespace llvm