#endif
}
-static bool OSHasAVXSupport() {\r
-#if defined(__GNUC__)\r
- // Check xgetbv; this uses a .byte sequence instead of the instruction \r
- // directly because older assemblers do not include support for xgetbv and \r
- // there is no easy way to conditionally compile based on the assembler used.\r
- int rEAX, rEDX;\r
- __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0));\r
-#elif defined(_MSC_FULL_VER) && _MSC_FULL_VER >= 160040219\r
- unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);\r
-#else\r
- int rEAX = 0; // Ensures we return false\r
-#endif\r
- return (rEAX & 6) == 6;\r
+static bool OSHasAVXSupport() {
+#if defined(__GNUC__)
+ // Check xgetbv; this uses a .byte sequence instead of the instruction
+ // directly because older assemblers do not include support for xgetbv and
+ // there is no easy way to conditionally compile based on the assembler used.
+ int rEAX, rEDX;
+ __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
+#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
+ unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
+#else
+ int rEAX = 0; // Ensures we return false
+#endif
+ return (rEAX & 6) == 6;
}
static void DetectX86FamilyModel(unsigned EAX, unsigned &Family,
// If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
// indicates that the AVX registers will be saved and restored on context
// switch, then we have full AVX support.
- bool HasAVX = (ECX & ((1 << 28) | (1 << 27))) != 0 && OSHasAVXSupport();
+ const unsigned AVXBits = (1 << 27) | (1 << 28);
+ bool HasAVX = ((ECX & AVXBits) == AVXBits) && OSHasAVXSupport();
GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
bool Em64T = (EDX >> 29) & 0x1;
case 20:
return "btver1";
case 21:
- if (Model <= 15)
- return "bdver1";
- else if (Model <= 31)
+ if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
+ return "btver1";
+ if (Model > 15 && Model <= 31)
return "bdver2";
+ return "bdver1";
+ case 22:
+ if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
+ return "btver1";
+ return "btver2";
default:
return "generic";
}
SmallVector<StringRef, 32> Lines;
Str.split(Lines, "\n");
- // Look for the CPU implementer line.
- StringRef Implementer;
- for (unsigned I = 0, E = Lines.size(); I != E; ++I)
- if (Lines[I].startswith("CPU implementer"))
- Implementer = Lines[I].substr(15).ltrim("\t :");
-
- if (Implementer == "0x41") { // ARM Ltd.
- SmallVector<StringRef, 32> CPUFeatures;
+ SmallVector<StringRef, 32> CPUFeatures;
- // Look for the CPU features.
- for (unsigned I = 0, E = Lines.size(); I != E; ++I)
- if (Lines[I].startswith("Features")) {
- Lines[I].split(CPUFeatures, " ");
- break;
- }
-
- for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
- StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
- .Case("half", "fp16")
- .Case("neon", "neon")
- .Case("vfpv3", "vfp3")
- .Case("vfpv3d16", "d16")
- .Case("vfpv4", "vfp4")
- .Case("idiva", "hwdiv-arm")
- .Case("idivt", "hwdiv")
- .Default("");
-
- if (LLVMFeatureStr != "")
- Features.GetOrCreateValue(LLVMFeatureStr).setValue(true);
+ // Look for the CPU features.
+ for (unsigned I = 0, E = Lines.size(); I != E; ++I)
+ if (Lines[I].startswith("Features")) {
+ Lines[I].split(CPUFeatures, " ");
+ break;
}
- return true;
+ for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
+ StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
+ .Case("half", "fp16")
+ .Case("neon", "neon")
+ .Case("vfpv3", "vfp3")
+ .Case("vfpv3d16", "d16")
+ .Case("vfpv4", "vfp4")
+ .Case("idiva", "hwdiv-arm")
+ .Case("idivt", "hwdiv")
+ .Default("");
+
+ if (LLVMFeatureStr != "")
+ Features.GetOrCreateValue(LLVMFeatureStr).setValue(true);
}
- return false;
+ return true;
}
#else
bool sys::getHostCPUFeatures(StringMap<bool> &Features){
#endif
std::string sys::getProcessTriple() {
- Triple PT(LLVM_HOSTTRIPLE);
+ Triple PT(LLVM_HOST_TRIPLE);
if (sizeof(void *) == 8 && PT.isArch32Bit())
PT = PT.get64BitArchVariant();