#endif
}
-static bool OSHasAVXSupport() {\r
-#if defined( __GNUC__ ) && \\r
- (__GNUC__ > 4 || __GNUC__ == 4 && __GNUC_MINOR__ >= 4)\r
- int rEAX, rEDX;\r
- __asm__ ("xgetbv" : "=a" (rEAX), "=d" (rEDX) : "c" (0)); \r
-#elif defined(_MSC_VER)\r
- unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);\r
-#else\r
- int rEAX = 0; // Ensures we return false\r
-#endif\r
- return (rEAX & 6) == 6;\r
+static bool OSHasAVXSupport() {
+#if defined(__GNUC__)
+ // Check xgetbv; this uses a .byte sequence instead of the instruction
+ // directly because older assemblers do not include support for xgetbv and
+ // there is no easy way to conditionally compile based on the assembler used.
+ int rEAX, rEDX;
+ __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
+#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
+ unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
+#else
+ int rEAX = 0; // Ensures we return false
+#endif
+ return (rEAX & 6) == 6;
}
static void DetectX86FamilyModel(unsigned EAX, unsigned &Family,
bool HasSSE3 = (ECX & 0x1);
// If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
// indicates that the AVX registers will be saved and restored on context
- // switch, when we have full AVX support.
- bool HasAVX = (ECX & ((1 << 28) | (1 << 27))) != 0 && OSHasAVXSupport();
+ // switch, then we have full AVX support.
+ const unsigned AVXBits = (1 << 27) | (1 << 28);
+ bool HasAVX = ((ECX & AVXBits) == AVXBits) && OSHasAVXSupport();
GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
bool Em64T = (EDX >> 29) & 0x1;