Init *BitRecTy::convertValue(TypedInit *VI) {
RecTy *Ty = VI->getType();
- if (isa<BitRecTy>(Ty) || isa<BitsRecTy>(Ty) || isa<IntRecTy>(Ty))
+ if (isa<BitRecTy>(Ty))
return VI; // Accept variable if it is already of bit type!
+ if (auto *BitsTy = dyn_cast<BitsRecTy>(Ty))
+ // Accept only bits<1> expression.
+ return BitsTy->getNumBits() == 1 ? VI : nullptr;
+ // Ternary !if can be converted to bit, but only if both sides are
+ // convertible to a bit.
+ if (TernOpInit *TOI = dyn_cast<TernOpInit>(VI)) {
+ if (TOI->getOpcode() != TernOpInit::TernaryOp::IF)
+ return nullptr;
+ if (!TOI->getMHS()->convertInitializerTo(BitRecTy::get()) ||
+ !TOI->getRHS()->convertInitializerTo(BitRecTy::get()))
+ return nullptr;
+ return TOI;
+ }
return nullptr;
}
break;
}
case ADD:
+ case AND:
case SHL:
case SRA:
case SRL: {
switch (getOpcode()) {
default: llvm_unreachable("Bad opcode!");
case ADD: Result = LHSv + RHSv; break;
+ case AND: Result = LHSv & RHSv; break;
case SHL: Result = LHSv << RHSv; break;
case SRA: Result = LHSv >> RHSv; break;
case SRL: Result = (uint64_t)LHSv >> (uint64_t)RHSv; break;
switch (Opc) {
case CONCAT: Result = "!con"; break;
case ADD: Result = "!add"; break;
+ case AND: Result = "!and"; break;
case SHL: Result = "!shl"; break;
case SRA: Result = "!sra"; break;
case SRL: Result = "!srl"; break;