#include "llvm/IR/Function.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/TargetRegistry.h"
-
#include <algorithm>
#define GET_INSTRINFO_CTOR_DTOR
.addImm(16);
return;
}
+ } else if (AArch64::FPR16RegClass.contains(DestReg, SrcReg)) {
+ // The copy of two FPR16 registers is implemented by the copy of two FPR32
+ const TargetRegisterInfo *TRI = &getRegisterInfo();
+ unsigned Dst = TRI->getMatchingSuperReg(DestReg, AArch64::sub_16,
+ &AArch64::FPR32RegClass);
+ unsigned Src = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_16,
+ &AArch64::FPR32RegClass);
+ BuildMI(MBB, I, DL, get(AArch64::FMOVss), Dst)
+ .addReg(Src);
+ return;
} else {
CopyPhysRegTuple(MBB, I, DL, DestReg, SrcReg);
return;
default:
llvm_unreachable("Unknown size for regclass");
}
- } else { // The spill of D tuples is implemented by Q tuples
- if (RC == &AArch64::QPairRegClass)
+ } else { // For a super register class has more than one sub registers
+ if (AArch64::DPairRegClass.hasSubClassEq(RC))
+ StoreOp = AArch64::ST1x2_8B;
+ else if (AArch64::DTripleRegClass.hasSubClassEq(RC))
+ StoreOp = AArch64::ST1x3_8B;
+ else if (AArch64::DQuadRegClass.hasSubClassEq(RC))
+ StoreOp = AArch64::ST1x4_8B;
+ else if (AArch64::QPairRegClass.hasSubClassEq(RC))
StoreOp = AArch64::ST1x2_16B;
- else if (RC == &AArch64::QTripleRegClass)
+ else if (AArch64::QTripleRegClass.hasSubClassEq(RC))
StoreOp = AArch64::ST1x3_16B;
- else if (RC == &AArch64::QQuadRegClass)
+ else if (AArch64::QQuadRegClass.hasSubClassEq(RC))
StoreOp = AArch64::ST1x4_16B;
else
llvm_unreachable("Unknown reg class");
default:
llvm_unreachable("Unknown size for regclass");
}
- } else { // The spill of D tuples is implemented by Q tuples
- if (RC == &AArch64::QPairRegClass)
+ } else { // For a super register class has more than one sub registers
+ if (AArch64::DPairRegClass.hasSubClassEq(RC))
+ LoadOp = AArch64::LD1x2_8B;
+ else if (AArch64::DTripleRegClass.hasSubClassEq(RC))
+ LoadOp = AArch64::LD1x3_8B;
+ else if (AArch64::DQuadRegClass.hasSubClassEq(RC))
+ LoadOp = AArch64::LD1x4_8B;
+ else if (AArch64::QPairRegClass.hasSubClassEq(RC))
LoadOp = AArch64::LD1x2_16B;
- else if (RC == &AArch64::QTripleRegClass)
+ else if (AArch64::QTripleRegClass.hasSubClassEq(RC))
LoadOp = AArch64::LD1x3_16B;
- else if (RC == &AArch64::QQuadRegClass)
+ else if (AArch64::QQuadRegClass.hasSubClassEq(RC))
LoadOp = AArch64::LD1x4_16B;
else
llvm_unreachable("Unknown reg class");
int &AccessScale, int &MinOffset,
int &MaxOffset) const {
switch (MI.getOpcode()) {
- default: llvm_unreachable("Unkown load/store kind");
+ default:
+ llvm_unreachable("Unknown load/store kind");
case TargetOpcode::DBG_VALUE:
AccessScale = 1;
MinOffset = INT_MIN;
MinOffset = -0x40 * AccessScale;
MaxOffset = 0x3f * AccessScale;
return;
+ case AArch64::LD1x2_8B: case AArch64::ST1x2_8B:
+ AccessScale = 16;
+ MinOffset = 0;
+ MaxOffset = 0xfff * AccessScale;
+ return;
+ case AArch64::LD1x3_8B: case AArch64::ST1x3_8B:
+ AccessScale = 24;
+ MinOffset = 0;
+ MaxOffset = 0xfff * AccessScale;
+ return;
+ case AArch64::LD1x4_8B: case AArch64::ST1x4_8B:
case AArch64::LD1x2_16B: case AArch64::ST1x2_16B:
AccessScale = 32;
MinOffset = 0;