+//===----- AArch64InstrInfo.td - AArch64 Instruction Info ----*- tablegen -*-=//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the AArch64 scalar instructions in TableGen format.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// ARM Instruction Predicate Definitions.
+//
+def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
+ AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
+def HasNEON : Predicate<"Subtarget->hasNEON()">,
+ AssemblerPredicate<"FeatureNEON", "neon">;
+def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
+ AssemblerPredicate<"FeatureCrypto","crypto">;
+
+// Use fused MAC if more precision in FP computation is allowed.
+def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
+ " FPOpFusion::Fast)">;
include "AArch64InstrFormats.td"
//===----------------------------------------------------------------------===//
def SDT_A64ret : SDTypeProfile<0, 0, []>;
def A64ret : SDNode<"AArch64ISD::Ret", SDT_A64ret, [SDNPHasChain,
- SDNPOptInGlue]>;
+ SDNPOptInGlue,
+ SDNPVariadic]>;
// (ins NZCV, Condition, Dest)
def SDT_A64br_cc : SDTypeProfile<0, 3, [SDTCisVT<0, i32>]>;
// made for a variable/address at ISelLowering.
// + The output of ISelLowering should be selectable (hence the Wrapper,
// rather than a bare target opcode)
-def SDTAArch64Wrapper : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
- SDTCisSameAs<1, 2>,
- SDTCisVT<3, i32>,
- SDTCisPtrTy<0>]>;
+def SDTAArch64WrapperLarge : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
+ SDTCisSameAs<0, 2>,
+ SDTCisSameAs<0, 3>,
+ SDTCisSameAs<0, 4>,
+ SDTCisPtrTy<0>]>;
+
+def A64WrapperLarge :SDNode<"AArch64ISD::WrapperLarge", SDTAArch64WrapperLarge>;
-def A64WrapperSmall : SDNode<"AArch64ISD::WrapperSmall", SDTAArch64Wrapper>;
+def SDTAArch64WrapperSmall : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
+ SDTCisSameAs<1, 2>,
+ SDTCisVT<3, i32>,
+ SDTCisPtrTy<0>]>;
+
+def A64WrapperSmall :SDNode<"AArch64ISD::WrapperSmall", SDTAArch64WrapperSmall>;
def SDTAArch64GOTLoad : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
def A64Ubfx : SDNode<"AArch64ISD::UBFX", SDTA64BFX>;
+class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
+
//===----------------------------------------------------------------------===//
// Call sequence pseudo-instructions
//===----------------------------------------------------------------------===//
def SDTTLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
def A64tlsdesc_blr : SDNode<"AArch64ISD::TLSDESCCALL", SDTTLSDescCall,
- [SDNPInGlue, SDNPOutGlue, SDNPHasChain, SDNPVariadic]>;
+ [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
+ SDNPVariadic]>;
def SDT_AArch64CallSeqStart : SDCallSeqStart<[ SDTCisPtrTy<0> ]>;
// arguments passed on the stack. Here we select those markers to
// pseudo-instructions which explicitly set the stack, and finally in the
// RegisterInfo we convert them to a true stack adjustment.
-let Defs = [XSP], Uses = [XSP] in
-{
+let Defs = [XSP], Uses = [XSP] in {
def ADJCALLSTACKDOWN : PseudoInst<(outs), (ins i64imm:$amt),
[(AArch64callseq_start timm:$amt)]>;
// Atomic operation pseudo-instructions
//===----------------------------------------------------------------------===//
-let usesCustomInserter = 1, Defs = [NZCV] in {
-multiclass AtomicSizes<string opname>
-{
- def _I8 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$incr),
- [(set GPR32:$dst, (!cast<SDNode>(opname # "_8") GPR64:$ptr, GPR32:$incr))]>;
- def _I16 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$incr),
- [(set GPR32:$dst, (!cast<SDNode>(opname # "_16") GPR64:$ptr, GPR32:$incr))]>;
- def _I32 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$incr),
- [(set GPR32:$dst, (!cast<SDNode>(opname # "_32") GPR64:$ptr, GPR32:$incr))]>;
- def _I64 : PseudoInst<(outs GPR64:$dst), (ins GPR64:$ptr, GPR64:$incr),
- [(set GPR64:$dst, (!cast<SDNode>(opname # "_64") GPR64:$ptr, GPR64:$incr))]>;
-}
-}
-
-defm ATOMIC_LOAD_ADD : AtomicSizes<"atomic_load_add">;
-defm ATOMIC_LOAD_SUB : AtomicSizes<"atomic_load_sub">;
-defm ATOMIC_LOAD_AND : AtomicSizes<"atomic_load_and">;
-defm ATOMIC_LOAD_OR : AtomicSizes<"atomic_load_or">;
-defm ATOMIC_LOAD_XOR : AtomicSizes<"atomic_load_xor">;
-defm ATOMIC_LOAD_NAND : AtomicSizes<"atomic_load_nand">;
-defm ATOMIC_LOAD_MIN : AtomicSizes<"atomic_load_min">;
-defm ATOMIC_LOAD_MAX : AtomicSizes<"atomic_load_max">;
-defm ATOMIC_LOAD_UMIN : AtomicSizes<"atomic_load_umin">;
-defm ATOMIC_LOAD_UMAX : AtomicSizes<"atomic_load_umax">;
-defm ATOMIC_SWAP : AtomicSizes<"atomic_swap">;
-
-let usesCustomInserter = 1, Defs = [NZCV] in {
-def ATOMIC_CMP_SWAP_I8
- : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$old, GPR32:$new),
- [(set GPR32:$dst,
- (atomic_cmp_swap_8 GPR64:$ptr, GPR32:$old, GPR32:$new))]>;
-def ATOMIC_CMP_SWAP_I16
- : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$old, GPR32:$new),
- [(set GPR32:$dst,
- (atomic_cmp_swap_16 GPR64:$ptr, GPR32:$old, GPR32:$new))]>;
-def ATOMIC_CMP_SWAP_I32
- : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$old, GPR32:$new),
- [(set GPR32:$dst,
- (atomic_cmp_swap_32 GPR64:$ptr, GPR32:$old, GPR32:$new))]>;
-def ATOMIC_CMP_SWAP_I64
- : PseudoInst<(outs GPR64:$dst), (ins GPR64:$ptr, GPR64:$old, GPR64:$new),
- [(set GPR64:$dst,
- (atomic_cmp_swap_64 GPR64:$ptr, GPR64:$old, GPR64:$new))]>;
+// These get selected from C++ code as a pretty much direct translation from the
+// generic DAG nodes. The one exception is the AtomicOrdering is added as an
+// operand so that the eventual lowering can make use of it and choose
+// acquire/release operations when required.
+
+let usesCustomInserter = 1, hasCtrlDep = 1, mayLoad = 1, mayStore = 1 in {
+multiclass AtomicSizes {
+ def _I8 : PseudoInst<(outs GPR32:$dst),
+ (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
+ def _I16 : PseudoInst<(outs GPR32:$dst),
+ (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
+ def _I32 : PseudoInst<(outs GPR32:$dst),
+ (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
+ def _I64 : PseudoInst<(outs GPR64:$dst),
+ (ins GPR64xsp:$ptr, GPR64:$incr, i32imm:$ordering), []>;
+}
+}
+
+defm ATOMIC_LOAD_ADD : AtomicSizes;
+defm ATOMIC_LOAD_SUB : AtomicSizes;
+defm ATOMIC_LOAD_AND : AtomicSizes;
+defm ATOMIC_LOAD_OR : AtomicSizes;
+defm ATOMIC_LOAD_XOR : AtomicSizes;
+defm ATOMIC_LOAD_NAND : AtomicSizes;
+defm ATOMIC_SWAP : AtomicSizes;
+let Defs = [NZCV] in {
+ // These operations need a CMP to calculate the correct value
+ defm ATOMIC_LOAD_MIN : AtomicSizes;
+ defm ATOMIC_LOAD_MAX : AtomicSizes;
+ defm ATOMIC_LOAD_UMIN : AtomicSizes;
+ defm ATOMIC_LOAD_UMAX : AtomicSizes;
}
+class AtomicCmpSwap<RegisterClass GPRData>
+ : PseudoInst<(outs GPRData:$dst),
+ (ins GPR64xsp:$ptr, GPRData:$old, GPRData:$new,
+ i32imm:$ordering), []> {
+ let usesCustomInserter = 1;
+ let hasCtrlDep = 1;
+ let mayLoad = 1;
+ let mayStore = 1;
+ let Defs = [NZCV];
+}
+
+def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<GPR32>;
+def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<GPR32>;
+def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<GPR32>;
+def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<GPR64>;
+
//===----------------------------------------------------------------------===//
// Add-subtract (extended register) instructions
//===----------------------------------------------------------------------===//
// is not optional in that case (but can explicitly be 0), and the
// entire suffix can be skipped (e.g. "add sp, x3, x2").
-multiclass extend_operands<string PREFIX>
-{
- def _asmoperand : AsmOperandClass
- {
+multiclass extend_operands<string PREFIX, string Diag> {
+ def _asmoperand : AsmOperandClass {
let Name = PREFIX;
let RenderMethod = "addRegExtendOperands";
let PredicateMethod = "isRegExtend<A64SE::" # PREFIX # ">";
+ let DiagnosticType = "AddSubRegExtend" # Diag;
}
- def _operand : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 4; }]>
- {
+ def _operand : Operand<i64>,
+ ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 4; }]> {
let PrintMethod = "printRegExtendOperand<A64SE::" # PREFIX # ">";
let DecoderMethod = "DecodeRegExtendOperand";
let ParserMatchClass = !cast<AsmOperandClass>(PREFIX # "_asmoperand");
}
}
-defm UXTB : extend_operands<"UXTB">;
-defm UXTH : extend_operands<"UXTH">;
-defm UXTW : extend_operands<"UXTW">;
-defm UXTX : extend_operands<"UXTX">;
-defm SXTB : extend_operands<"SXTB">;
-defm SXTH : extend_operands<"SXTH">;
-defm SXTW : extend_operands<"SXTW">;
-defm SXTX : extend_operands<"SXTX">;
+defm UXTB : extend_operands<"UXTB", "Small">;
+defm UXTH : extend_operands<"UXTH", "Small">;
+defm UXTW : extend_operands<"UXTW", "Small">;
+defm UXTX : extend_operands<"UXTX", "Large">;
+defm SXTB : extend_operands<"SXTB", "Small">;
+defm SXTH : extend_operands<"SXTH", "Small">;
+defm SXTW : extend_operands<"SXTW", "Small">;
+defm SXTX : extend_operands<"SXTX", "Large">;
-def LSL_extasmoperand : AsmOperandClass
-{
+def LSL_extasmoperand : AsmOperandClass {
let Name = "RegExtendLSL";
let RenderMethod = "addRegExtendOperands";
+ let DiagnosticType = "AddSubRegExtendLarge";
}
-def LSL_extoperand : Operand<i64>
-{
+def LSL_extoperand : Operand<i64> {
let ParserMatchClass = LSL_extasmoperand;
}
// non-uniform because everything has already been promoted to the
// legal i64 and i32 types. We'll wrap the various variants up in a
// class for use later.
-class extend_types
-{
+class extend_types {
dag uxtb; dag uxth; dag uxtw; dag uxtx;
dag sxtb; dag sxth; dag sxtw; dag sxtx;
+ ValueType ty;
+ RegisterClass GPR;
}
-def extends_to_i64 : extend_types
-{
- let uxtb = (and (anyext GPR32:$Rm), 255);
- let uxth = (and (anyext GPR32:$Rm), 65535);
- let uxtw = (zext GPR32:$Rm);
- let uxtx = (i64 GPR64:$Rm);
+def extends_to_i64 : extend_types {
+ let uxtb = (and (anyext i32:$Rm), 255);
+ let uxth = (and (anyext i32:$Rm), 65535);
+ let uxtw = (zext i32:$Rm);
+ let uxtx = (i64 $Rm);
+
+ let sxtb = (sext_inreg (anyext i32:$Rm), i8);
+ let sxth = (sext_inreg (anyext i32:$Rm), i16);
+ let sxtw = (sext i32:$Rm);
+ let sxtx = (i64 $Rm);
- let sxtb = (sext_inreg (anyext GPR32:$Rm), i8);
- let sxth = (sext_inreg (anyext GPR32:$Rm), i16);
- let sxtw = (sext GPR32:$Rm);
- let sxtx = (i64 GPR64:$Rm);
+ let ty = i64;
+ let GPR = GPR64xsp;
}
-def extends_to_i32 : extend_types
-{
- let uxtb = (and GPR32:$Rm, 255);
- let uxth = (and GPR32:$Rm, 65535);
- let uxtw = (i32 GPR32:$Rm);
- let uxtx = (i32 GPR32:$Rm);
+def extends_to_i32 : extend_types {
+ let uxtb = (and i32:$Rm, 255);
+ let uxth = (and i32:$Rm, 65535);
+ let uxtw = (i32 i32:$Rm);
+ let uxtx = (i32 i32:$Rm);
- let sxtb = (sext_inreg GPR32:$Rm, i8);
- let sxth = (sext_inreg GPR32:$Rm, i16);
- let sxtw = (i32 GPR32:$Rm);
- let sxtx = (i32 GPR32:$Rm);
+ let sxtb = (sext_inreg i32:$Rm, i8);
+ let sxth = (sext_inreg i32:$Rm, i16);
+ let sxtw = (i32 i32:$Rm);
+ let sxtx = (i32 i32:$Rm);
+
+ let ty = i32;
+ let GPR = GPR32wsp;
}
// Now, six of the extensions supported are easy and uniform: if the source size
// + Patterns are very different as well.
// + Passing different registers would be ugly (more fields in extend_types
// would probably be the best option).
-multiclass addsub_exts<bit sf, bit op, bit S, string asmop, SDPatternOperator opfrag,
- dag outs, extend_types exts, RegisterClass GPRsp>
-{
+multiclass addsub_exts<bit sf, bit op, bit S, string asmop,
+ SDPatternOperator opfrag,
+ dag outs, extend_types exts> {
def w_uxtb : A64I_addsubext<sf, op, S, 0b00, 0b000,
- outs,
- (ins GPRsp:$Rn, GPR32:$Rm, UXTB_operand:$Imm3),
- !strconcat(asmop, "$Rn, $Rm, $Imm3"),
- [(opfrag GPRsp:$Rn, (shl exts.uxtb, UXTB_operand:$Imm3))],
- NoItinerary>;
+ outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTB_operand:$Imm3),
+ !strconcat(asmop, "$Rn, $Rm, $Imm3"),
+ [(opfrag exts.ty:$Rn, (shl exts.uxtb, UXTB_operand:$Imm3))],
+ NoItinerary>;
def w_uxth : A64I_addsubext<sf, op, S, 0b00, 0b001,
- outs,
- (ins GPRsp:$Rn, GPR32:$Rm, UXTH_operand:$Imm3),
- !strconcat(asmop, "$Rn, $Rm, $Imm3"),
- [(opfrag GPRsp:$Rn, (shl exts.uxth, UXTH_operand:$Imm3))],
- NoItinerary>;
+ outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTH_operand:$Imm3),
+ !strconcat(asmop, "$Rn, $Rm, $Imm3"),
+ [(opfrag exts.ty:$Rn, (shl exts.uxth, UXTH_operand:$Imm3))],
+ NoItinerary>;
def w_uxtw : A64I_addsubext<sf, op, S, 0b00, 0b010,
- outs,
- (ins GPRsp:$Rn, GPR32:$Rm, UXTW_operand:$Imm3),
- !strconcat(asmop, "$Rn, $Rm, $Imm3"),
- [(opfrag GPRsp:$Rn, (shl exts.uxtw, UXTW_operand:$Imm3))],
- NoItinerary>;
+ outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTW_operand:$Imm3),
+ !strconcat(asmop, "$Rn, $Rm, $Imm3"),
+ [(opfrag exts.ty:$Rn, (shl exts.uxtw, UXTW_operand:$Imm3))],
+ NoItinerary>;
def w_sxtb : A64I_addsubext<sf, op, S, 0b00, 0b100,
- outs,
- (ins GPRsp:$Rn, GPR32:$Rm, SXTB_operand:$Imm3),
- !strconcat(asmop, "$Rn, $Rm, $Imm3"),
- [(opfrag GPRsp:$Rn, (shl exts.sxtb, SXTB_operand:$Imm3))],
- NoItinerary>;
+ outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTB_operand:$Imm3),
+ !strconcat(asmop, "$Rn, $Rm, $Imm3"),
+ [(opfrag exts.ty:$Rn, (shl exts.sxtb, SXTB_operand:$Imm3))],
+ NoItinerary>;
def w_sxth : A64I_addsubext<sf, op, S, 0b00, 0b101,
- outs,
- (ins GPRsp:$Rn, GPR32:$Rm, SXTH_operand:$Imm3),
- !strconcat(asmop, "$Rn, $Rm, $Imm3"),
- [(opfrag GPRsp:$Rn, (shl exts.sxth, SXTH_operand:$Imm3))],
- NoItinerary>;
+ outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTH_operand:$Imm3),
+ !strconcat(asmop, "$Rn, $Rm, $Imm3"),
+ [(opfrag exts.ty:$Rn, (shl exts.sxth, SXTH_operand:$Imm3))],
+ NoItinerary>;
def w_sxtw : A64I_addsubext<sf, op, S, 0b00, 0b110,
- outs,
- (ins GPRsp:$Rn, GPR32:$Rm, SXTW_operand:$Imm3),
- !strconcat(asmop, "$Rn, $Rm, $Imm3"),
- [(opfrag GPRsp:$Rn, (shl exts.sxtw, SXTW_operand:$Imm3))],
- NoItinerary>;
+ outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTW_operand:$Imm3),
+ !strconcat(asmop, "$Rn, $Rm, $Imm3"),
+ [(opfrag exts.ty:$Rn, (shl exts.sxtw, SXTW_operand:$Imm3))],
+ NoItinerary>;
}
// These two could be merge in with the above, but their patterns aren't really
// necessary and the naming-scheme would necessarily break:
-multiclass addsub_xxtx<bit op, bit S, string asmop, SDPatternOperator opfrag, dag outs>
-{
+multiclass addsub_xxtx<bit op, bit S, string asmop, SDPatternOperator opfrag,
+ dag outs> {
def x_uxtx : A64I_addsubext<0b1, op, S, 0b00, 0b011,
outs,
(ins GPR64xsp:$Rn, GPR64:$Rm, UXTX_operand:$Imm3),
!strconcat(asmop, "$Rn, $Rm, $Imm3"),
- [(opfrag GPR64xsp:$Rn, (shl GPR64:$Rm, UXTX_operand:$Imm3))],
+ [(opfrag i64:$Rn, (shl i64:$Rm, UXTX_operand:$Imm3))],
NoItinerary>;
def x_sxtx : A64I_addsubext<0b1, op, S, 0b00, 0b111,
NoItinerary>;
}
-multiclass addsub_wxtx<bit op, bit S, string asmop, dag outs>
-{
+multiclass addsub_wxtx<bit op, bit S, string asmop, dag outs> {
def w_uxtx : A64I_addsubext<0b0, op, S, 0b00, 0b011,
outs,
(ins GPR32wsp:$Rn, GPR32:$Rm, UXTX_operand:$Imm3),
: PatFrag<(ops node:$lhs, node:$rhs), (set NZCV, (op node:$lhs, node:$rhs))>;
defm ADDxx :addsub_exts<0b1, 0b0, 0b0, "add\t$Rd, ", SetRD<GPR64xsp, add>,
- (outs GPR64xsp:$Rd), extends_to_i64, GPR64xsp>,
+ (outs GPR64xsp:$Rd), extends_to_i64>,
addsub_xxtx< 0b0, 0b0, "add\t$Rd, ", SetRD<GPR64xsp, add>,
(outs GPR64xsp:$Rd)>;
defm ADDww :addsub_exts<0b0, 0b0, 0b0, "add\t$Rd, ", SetRD<GPR32wsp, add>,
- (outs GPR32wsp:$Rd), extends_to_i32, GPR32wsp>,
+ (outs GPR32wsp:$Rd), extends_to_i32>,
addsub_wxtx< 0b0, 0b0, "add\t$Rd, ",
(outs GPR32wsp:$Rd)>;
defm SUBxx :addsub_exts<0b1, 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR64xsp, sub>,
- (outs GPR64xsp:$Rd), extends_to_i64, GPR64xsp>,
+ (outs GPR64xsp:$Rd), extends_to_i64>,
addsub_xxtx< 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR64xsp, sub>,
(outs GPR64xsp:$Rd)>;
defm SUBww :addsub_exts<0b0, 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR32wsp, sub>,
- (outs GPR32wsp:$Rd), extends_to_i32, GPR32wsp>,
+ (outs GPR32wsp:$Rd), extends_to_i32>,
addsub_wxtx< 0b1, 0b0, "sub\t$Rd, ",
(outs GPR32wsp:$Rd)>;
let Defs = [NZCV] in {
defm ADDSxx :addsub_exts<0b1, 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR64, addc>,
- (outs GPR64:$Rd), extends_to_i64, GPR64xsp>,
+ (outs GPR64:$Rd), extends_to_i64>,
addsub_xxtx< 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR64, addc>,
(outs GPR64:$Rd)>;
defm ADDSww :addsub_exts<0b0, 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR32, addc>,
- (outs GPR32:$Rd), extends_to_i32, GPR32wsp>,
+ (outs GPR32:$Rd), extends_to_i32>,
addsub_wxtx< 0b0, 0b1, "adds\t$Rd, ",
(outs GPR32:$Rd)>;
defm SUBSxx :addsub_exts<0b1, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>,
- (outs GPR64:$Rd), extends_to_i64, GPR64xsp>,
+ (outs GPR64:$Rd), extends_to_i64>,
addsub_xxtx< 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>,
(outs GPR64:$Rd)>;
defm SUBSww :addsub_exts<0b0, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR32, subc>,
- (outs GPR32:$Rd), extends_to_i32, GPR32wsp>,
+ (outs GPR32:$Rd), extends_to_i32>,
addsub_wxtx< 0b1, 0b1, "subs\t$Rd, ",
(outs GPR32:$Rd)>;
let Rd = 0b11111, isCompare = 1 in {
defm CMNx : addsub_exts<0b1, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>,
- (outs), extends_to_i64, GPR64xsp>,
+ (outs), extends_to_i64>,
addsub_xxtx< 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>, (outs)>;
defm CMNw : addsub_exts<0b0, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>,
- (outs), extends_to_i32, GPR32wsp>,
+ (outs), extends_to_i32>,
addsub_wxtx< 0b0, 0b1, "cmn\t", (outs)>;
defm CMPx : addsub_exts<0b1, 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>,
- (outs), extends_to_i64, GPR64xsp>,
+ (outs), extends_to_i64>,
addsub_xxtx< 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>, (outs)>;
defm CMPw : addsub_exts<0b0, 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>,
- (outs), extends_to_i32, GPR32wsp>,
+ (outs), extends_to_i32>,
addsub_wxtx< 0b1, 0b1, "cmp\t", (outs)>;
}
}
// created for uxtx/sxtx since they're non-uniform and it's expected that
// add/sub (shifted register) will handle those cases anyway.
multiclass addsubext_noshift_patterns<string prefix, SDPatternOperator nodeop,
- RegisterClass GPRsp, extend_types exts>
-{
- def : Pat<(nodeop GPRsp:$Rn, exts.uxtb),
- (!cast<Instruction>(prefix # "w_uxtb") GPRsp:$Rn, GPR32:$Rm, 0)>;
- def : Pat<(nodeop GPRsp:$Rn, exts.uxth),
- (!cast<Instruction>(prefix # "w_uxth") GPRsp:$Rn, GPR32:$Rm, 0)>;
- def : Pat<(nodeop GPRsp:$Rn, exts.uxtw),
- (!cast<Instruction>(prefix # "w_uxtw") GPRsp:$Rn, GPR32:$Rm, 0)>;
-
- def : Pat<(nodeop GPRsp:$Rn, exts.sxtb),
- (!cast<Instruction>(prefix # "w_sxtb") GPRsp:$Rn, GPR32:$Rm, 0)>;
- def : Pat<(nodeop GPRsp:$Rn, exts.sxth),
- (!cast<Instruction>(prefix # "w_sxth") GPRsp:$Rn, GPR32:$Rm, 0)>;
- def : Pat<(nodeop GPRsp:$Rn, exts.sxtw),
- (!cast<Instruction>(prefix # "w_sxtw") GPRsp:$Rn, GPR32:$Rm, 0)>;
-}
-
-defm : addsubext_noshift_patterns<"ADDxx", add, GPR64xsp, extends_to_i64>;
-defm : addsubext_noshift_patterns<"ADDww", add, GPR32wsp, extends_to_i32>;
-defm : addsubext_noshift_patterns<"SUBxx", sub, GPR64xsp, extends_to_i64>;
-defm : addsubext_noshift_patterns<"SUBww", sub, GPR32wsp, extends_to_i32>;
-
-defm : addsubext_noshift_patterns<"CMNx", A64cmn, GPR64xsp, extends_to_i64>;
-defm : addsubext_noshift_patterns<"CMNw", A64cmn, GPR32wsp, extends_to_i32>;
-defm : addsubext_noshift_patterns<"CMPx", A64cmp, GPR64xsp, extends_to_i64>;
-defm : addsubext_noshift_patterns<"CMPw", A64cmp, GPR32wsp, extends_to_i32>;
+ extend_types exts> {
+ def : Pat<(nodeop exts.ty:$Rn, exts.uxtb),
+ (!cast<Instruction>(prefix # "w_uxtb") $Rn, $Rm, 0)>;
+ def : Pat<(nodeop exts.ty:$Rn, exts.uxth),
+ (!cast<Instruction>(prefix # "w_uxth") $Rn, $Rm, 0)>;
+ def : Pat<(nodeop exts.ty:$Rn, exts.uxtw),
+ (!cast<Instruction>(prefix # "w_uxtw") $Rn, $Rm, 0)>;
+
+ def : Pat<(nodeop exts.ty:$Rn, exts.sxtb),
+ (!cast<Instruction>(prefix # "w_sxtb") $Rn, $Rm, 0)>;
+ def : Pat<(nodeop exts.ty:$Rn, exts.sxth),
+ (!cast<Instruction>(prefix # "w_sxth") $Rn, $Rm, 0)>;
+ def : Pat<(nodeop exts.ty:$Rn, exts.sxtw),
+ (!cast<Instruction>(prefix # "w_sxtw") $Rn, $Rm, 0)>;
+}
+
+defm : addsubext_noshift_patterns<"ADDxx", add, extends_to_i64>;
+defm : addsubext_noshift_patterns<"ADDww", add, extends_to_i32>;
+defm : addsubext_noshift_patterns<"SUBxx", sub, extends_to_i64>;
+defm : addsubext_noshift_patterns<"SUBww", sub, extends_to_i32>;
+
+defm : addsubext_noshift_patterns<"CMNx", A64cmn, extends_to_i64>;
+defm : addsubext_noshift_patterns<"CMNw", A64cmn, extends_to_i32>;
+defm : addsubext_noshift_patterns<"CMPx", A64cmp, extends_to_i64>;
+defm : addsubext_noshift_patterns<"CMPw", A64cmp, extends_to_i32>;
// An extend of "lsl #imm" is valid if and only if one of Rn and Rd is
// sp/wsp. It is synonymous with uxtx/uxtw depending on the size of the
// operation. Also permitted in this case is complete omission of the argument,
// which implies "lsl #0".
multiclass lsl_aliases<string asmop, Instruction inst, RegisterClass GPR_Rd,
- RegisterClass GPR_Rn, RegisterClass GPR_Rm>
-{
+ RegisterClass GPR_Rn, RegisterClass GPR_Rm> {
def : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"),
(inst GPR_Rd:$Rd, GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>;
// CMP unfortunately has to be different because the instruction doesn't have a
// dest register.
multiclass cmp_lsl_aliases<string asmop, Instruction inst,
- RegisterClass GPR_Rn, RegisterClass GPR_Rm>
-{
+ RegisterClass GPR_Rn, RegisterClass GPR_Rm> {
def : InstAlias<!strconcat(asmop, " $Rn, $Rm"),
(inst GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>;
// should be parsed: there was no way to accommodate an "lsl #12".
let ParserMethod = "ParseImmWithLSLOperand",
- RenderMethod = "addImmWithLSLOperands" in
-{
+ RenderMethod = "addImmWithLSLOperands" in {
// Derived PredicateMethod fields are different for each
- def addsubimm_lsl0_asmoperand : AsmOperandClass
- {
+ def addsubimm_lsl0_asmoperand : AsmOperandClass {
let Name = "AddSubImmLSL0";
+ // If an error is reported against this operand, instruction could also be a
+ // register variant.
+ let DiagnosticType = "AddSubSecondSource";
}
- def addsubimm_lsl12_asmoperand : AsmOperandClass
- {
+ def addsubimm_lsl12_asmoperand : AsmOperandClass {
let Name = "AddSubImmLSL12";
+ let DiagnosticType = "AddSubSecondSource";
}
}
}]>;
-multiclass addsub_imm_operands<ValueType ty>
-{
+multiclass addsub_imm_operands<ValueType ty> {
let PrintMethod = "printAddSubImmLSL0Operand",
EncoderMethod = "getAddSubImmOpValue",
- ParserMatchClass = addsubimm_lsl0_asmoperand in
- {
+ ParserMatchClass = addsubimm_lsl0_asmoperand in {
def _posimm_lsl0 : Operand<ty>,
ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff) == 0; }]>;
def _negimm_lsl0 : Operand<ty>,
let PrintMethod = "printAddSubImmLSL12Operand",
EncoderMethod = "getAddSubImmOpValue",
- ParserMatchClass = addsubimm_lsl12_asmoperand in
- {
+ ParserMatchClass = addsubimm_lsl12_asmoperand in {
def _posimm_lsl12 : Operand<ty>,
ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff000) == 0; }],
shr_12_XFORM>;
string asmop, string cmpasmop,
Operand imm_operand, Operand cmp_imm_operand,
RegisterClass GPR, RegisterClass GPRsp,
- AArch64Reg ZR>
-{
+ AArch64Reg ZR, ValueType Ty> {
// All registers for non-S variants allow SP
def _s : A64I_addsubimm<sf, op, 0b0, shift,
(outs GPRsp:$Rd),
(ins GPRsp:$Rn, imm_operand:$Imm12),
!strconcat(asmop, "\t$Rd, $Rn, $Imm12"),
- [(set GPRsp:$Rd,
- (add GPRsp:$Rn, imm_operand:$Imm12))],
+ [(set Ty:$Rd, (add Ty:$Rn, imm_operand:$Imm12))],
NoItinerary>;
(outs GPR:$Rd),
(ins GPRsp:$Rn, imm_operand:$Imm12),
!strconcat(asmop, "s\t$Rd, $Rn, $Imm12"),
- [(set GPR:$Rd, (addc GPRsp:$Rn, imm_operand:$Imm12))],
+ [(set Ty:$Rd, (addc Ty:$Rn, imm_operand:$Imm12))],
NoItinerary> {
let Defs = [NZCV];
}
(outs), (ins GPRsp:$Rn, imm_operand:$Imm12),
!strconcat(cmpasmop, " $Rn, $Imm12"),
[(set NZCV,
- (A64cmp GPRsp:$Rn, cmp_imm_operand:$Imm12))],
- NoItinerary>
- {
+ (A64cmp Ty:$Rn, cmp_imm_operand:$Imm12))],
+ NoItinerary> {
let Rd = 0b11111;
let Defs = [NZCV];
let isCompare = 1;
multiclass addsubimm_shifts<string prefix, bit sf, bit op,
string asmop, string cmpasmop, string operand, string cmpoperand,
- RegisterClass GPR, RegisterClass GPRsp, AArch64Reg ZR>
-{
+ RegisterClass GPR, RegisterClass GPRsp, AArch64Reg ZR,
+ ValueType Ty> {
defm _lsl0 : addsubimm_varieties<prefix # "_lsl0", sf, op, 0b00,
asmop, cmpasmop,
!cast<Operand>(operand # "_lsl0"),
!cast<Operand>(cmpoperand # "_lsl0"),
- GPR, GPRsp, ZR>;
+ GPR, GPRsp, ZR, Ty>;
defm _lsl12 : addsubimm_varieties<prefix # "_lsl12", sf, op, 0b01,
asmop, cmpasmop,
!cast<Operand>(operand # "_lsl12"),
!cast<Operand>(cmpoperand # "_lsl12"),
- GPR, GPRsp, ZR>;
+ GPR, GPRsp, ZR, Ty>;
}
defm ADDwwi : addsubimm_shifts<"ADDwi", 0b0, 0b0, "add", "cmn",
"addsubimm_operand_i32_posimm",
"addsubimm_operand_i32_negimm",
- GPR32, GPR32wsp, WZR>;
+ GPR32, GPR32wsp, WZR, i32>;
defm ADDxxi : addsubimm_shifts<"ADDxi", 0b1, 0b0, "add", "cmn",
"addsubimm_operand_i64_posimm",
"addsubimm_operand_i64_negimm",
- GPR64, GPR64xsp, XZR>;
+ GPR64, GPR64xsp, XZR, i64>;
defm SUBwwi : addsubimm_shifts<"SUBwi", 0b0, 0b1, "sub", "cmp",
"addsubimm_operand_i32_negimm",
"addsubimm_operand_i32_posimm",
- GPR32, GPR32wsp, WZR>;
+ GPR32, GPR32wsp, WZR, i32>;
defm SUBxxi : addsubimm_shifts<"SUBxi", 0b1, 0b1, "sub", "cmp",
"addsubimm_operand_i64_negimm",
"addsubimm_operand_i64_posimm",
- GPR64, GPR64xsp, XZR>;
+ GPR64, GPR64xsp, XZR, i64>;
-multiclass MOVsp<RegisterClass GPRsp, RegisterClass SP, Instruction addop>
-{
+multiclass MOVsp<RegisterClass GPRsp, RegisterClass SP, Instruction addop> {
def _fromsp : InstAlias<"mov $Rd, $Rn",
(addop GPRsp:$Rd, SP:$Rn, 0),
0b1>;
// 1. The "shifed register" operands. Shared with logical insts.
//===-------------------------------
-multiclass shift_operands<string prefix, string form>
-{
- def _asmoperand_i32 : AsmOperandClass
- {
+multiclass shift_operands<string prefix, string form> {
+ def _asmoperand_i32 : AsmOperandClass {
let Name = "Shift" # form # "i32";
let RenderMethod = "addShiftOperands";
- let PredicateMethod
- = "isShift<A64SE::" # form # ", false>";
+ let PredicateMethod = "isShift<A64SE::" # form # ", false>";
+ let DiagnosticType = "AddSubRegShift32";
}
// Note that the operand type is intentionally i64 because the DAGCombiner
// puts these into a canonical form.
- def _i32 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]>
- {
+ def _i32 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
let ParserMatchClass
= !cast<AsmOperandClass>(prefix # "_asmoperand_i32");
let PrintMethod = "printShiftOperand<A64SE::" # form # ">";
let DecoderMethod = "Decode32BitShiftOperand";
}
- def _asmoperand_i64 : AsmOperandClass
- {
+ def _asmoperand_i64 : AsmOperandClass {
let Name = "Shift" # form # "i64";
let RenderMethod = "addShiftOperands";
- let PredicateMethod
- = "isShift<A64SE::" # form # ", true>";
+ let PredicateMethod = "isShift<A64SE::" # form # ", true>";
+ let DiagnosticType = "AddSubRegShift64";
}
- def _i64 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]>
- {
+ def _i64 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
let ParserMatchClass
= !cast<AsmOperandClass>(prefix # "_asmoperand_i64");
let PrintMethod = "printShiftOperand<A64SE::" # form # ">";
// N.b. the commutable parameter is just !N. It will be first against the wall
// when the revolution comes.
multiclass addsub_shifts<string prefix, bit sf, bit op, bit s, bit commutable,
- string asmop, SDPatternOperator opfrag, string sty,
- RegisterClass GPR, list<Register> defs>
-{
+ string asmop, SDPatternOperator opfrag, ValueType ty,
+ RegisterClass GPR, list<Register> defs> {
let isCommutable = commutable, Defs = defs in {
def _lsl : A64I_addsubshift<sf, op, s, 0b00,
(outs GPR:$Rd),
(ins GPR:$Rn, GPR:$Rm,
- !cast<Operand>("lsl_operand_" # sty):$Imm6),
+ !cast<Operand>("lsl_operand_" # ty):$Imm6),
!strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
- [(set GPR:$Rd, (opfrag GPR:$Rn, (shl GPR:$Rm,
- !cast<Operand>("lsl_operand_" # sty):$Imm6))
+ [(set GPR:$Rd, (opfrag ty:$Rn, (shl ty:$Rm,
+ !cast<Operand>("lsl_operand_" # ty):$Imm6))
)],
NoItinerary>;
def _lsr : A64I_addsubshift<sf, op, s, 0b01,
(outs GPR:$Rd),
(ins GPR:$Rn, GPR:$Rm,
- !cast<Operand>("lsr_operand_" # sty):$Imm6),
+ !cast<Operand>("lsr_operand_" # ty):$Imm6),
!strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
- [(set GPR:$Rd, (opfrag GPR:$Rn, (srl GPR:$Rm,
- !cast<Operand>("lsr_operand_" # sty):$Imm6))
+ [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm,
+ !cast<Operand>("lsr_operand_" # ty):$Imm6))
)],
NoItinerary>;
def _asr : A64I_addsubshift<sf, op, s, 0b10,
(outs GPR:$Rd),
(ins GPR:$Rn, GPR:$Rm,
- !cast<Operand>("asr_operand_" # sty):$Imm6),
+ !cast<Operand>("asr_operand_" # ty):$Imm6),
!strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
- [(set GPR:$Rd, (opfrag GPR:$Rn, (sra GPR:$Rm,
- !cast<Operand>("asr_operand_" # sty):$Imm6))
+ [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm,
+ !cast<Operand>("asr_operand_" # ty):$Imm6))
)],
NoItinerary>;
}
(!cast<Instruction>(prefix # "_lsl") GPR:$Rd, GPR:$Rn,
GPR:$Rm, 0)>;
- def : Pat<(opfrag GPR:$Rn, GPR:$Rm),
- (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
+ def : Pat<(opfrag ty:$Rn, ty:$Rm),
+ (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
}
multiclass addsub_sizes<string prefix, bit op, bit s, bit commutable,
string asmop, SDPatternOperator opfrag,
- list<Register> defs>
-{
+ list<Register> defs> {
defm xxx : addsub_shifts<prefix # "xxx", 0b1, op, s,
- commutable, asmop, opfrag, "i64", GPR64, defs>;
+ commutable, asmop, opfrag, i64, GPR64, defs>;
defm www : addsub_shifts<prefix # "www", 0b0, op, s,
- commutable, asmop, opfrag, "i32", GPR32, defs>;
+ commutable, asmop, opfrag, i32, GPR32, defs>;
}
// 1. The NEG/NEGS aliases
//===-------------------------------
-multiclass neg_alias<Instruction INST, RegisterClass GPR,
- Register ZR, Operand shift_operand, SDNode shiftop>
-{
+multiclass neg_alias<Instruction INST, RegisterClass GPR, Register ZR,
+ ValueType ty, Operand shift_operand, SDNode shiftop> {
def : InstAlias<"neg $Rd, $Rm, $Imm6",
(INST GPR:$Rd, ZR, GPR:$Rm, shift_operand:$Imm6)>;
- def : Pat<(sub 0, (shiftop GPR:$Rm, shift_operand:$Imm6)),
- (INST ZR, GPR:$Rm, shift_operand:$Imm6)>;
+ def : Pat<(sub 0, (shiftop ty:$Rm, shift_operand:$Imm6)),
+ (INST ZR, $Rm, shift_operand:$Imm6)>;
}
-defm : neg_alias<SUBwww_lsl, GPR32, WZR, lsl_operand_i32, shl>;
-defm : neg_alias<SUBwww_lsr, GPR32, WZR, lsr_operand_i32, srl>;
-defm : neg_alias<SUBwww_asr, GPR32, WZR, asr_operand_i32, sra>;
+defm : neg_alias<SUBwww_lsl, GPR32, WZR, i32, lsl_operand_i32, shl>;
+defm : neg_alias<SUBwww_lsr, GPR32, WZR, i32, lsr_operand_i32, srl>;
+defm : neg_alias<SUBwww_asr, GPR32, WZR, i32, asr_operand_i32, sra>;
def : InstAlias<"neg $Rd, $Rm", (SUBwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>;
-def : Pat<(sub 0, GPR32:$Rm), (SUBwww_lsl WZR, GPR32:$Rm, 0)>;
+def : Pat<(sub 0, i32:$Rm), (SUBwww_lsl WZR, $Rm, 0)>;
-defm : neg_alias<SUBxxx_lsl, GPR64, XZR, lsl_operand_i64, shl>;
-defm : neg_alias<SUBxxx_lsr, GPR64, XZR, lsr_operand_i64, srl>;
-defm : neg_alias<SUBxxx_asr, GPR64, XZR, asr_operand_i64, sra>;
+defm : neg_alias<SUBxxx_lsl, GPR64, XZR, i64, lsl_operand_i64, shl>;
+defm : neg_alias<SUBxxx_lsr, GPR64, XZR, i64, lsr_operand_i64, srl>;
+defm : neg_alias<SUBxxx_asr, GPR64, XZR, i64, asr_operand_i64, sra>;
def : InstAlias<"neg $Rd, $Rm", (SUBxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>;
-def : Pat<(sub 0, GPR64:$Rm), (SUBxxx_lsl XZR, GPR64:$Rm, 0)>;
+def : Pat<(sub 0, i64:$Rm), (SUBxxx_lsl XZR, $Rm, 0)>;
// NEGS doesn't get any patterns yet: defining multiple outputs means C++ has to
// be involved.
//===-------------------------------
multiclass cmp_shifts<string prefix, bit sf, bit op, bit commutable,
- string asmop, SDPatternOperator opfrag, string sty,
- RegisterClass GPR>
-{
+ string asmop, SDPatternOperator opfrag, ValueType ty,
+ RegisterClass GPR> {
let isCommutable = commutable, Rd = 0b11111, Defs = [NZCV] in {
def _lsl : A64I_addsubshift<sf, op, 0b1, 0b00,
(outs),
(ins GPR:$Rn, GPR:$Rm,
- !cast<Operand>("lsl_operand_" # sty):$Imm6),
+ !cast<Operand>("lsl_operand_" # ty):$Imm6),
!strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
- [(set NZCV, (opfrag GPR:$Rn, (shl GPR:$Rm,
- !cast<Operand>("lsl_operand_" # sty):$Imm6))
+ [(set NZCV, (opfrag ty:$Rn, (shl ty:$Rm,
+ !cast<Operand>("lsl_operand_" # ty):$Imm6))
)],
NoItinerary>;
def _lsr : A64I_addsubshift<sf, op, 0b1, 0b01,
(outs),
(ins GPR:$Rn, GPR:$Rm,
- !cast<Operand>("lsr_operand_" # sty):$Imm6),
+ !cast<Operand>("lsr_operand_" # ty):$Imm6),
!strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
- [(set NZCV, (opfrag GPR:$Rn, (srl GPR:$Rm,
- !cast<Operand>("lsr_operand_" # sty):$Imm6))
+ [(set NZCV, (opfrag ty:$Rn, (srl ty:$Rm,
+ !cast<Operand>("lsr_operand_" # ty):$Imm6))
)],
NoItinerary>;
def _asr : A64I_addsubshift<sf, op, 0b1, 0b10,
(outs),
(ins GPR:$Rn, GPR:$Rm,
- !cast<Operand>("asr_operand_" # sty):$Imm6),
+ !cast<Operand>("asr_operand_" # ty):$Imm6),
!strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
- [(set NZCV, (opfrag GPR:$Rn, (sra GPR:$Rm,
- !cast<Operand>("asr_operand_" # sty):$Imm6))
+ [(set NZCV, (opfrag ty:$Rn, (sra ty:$Rm,
+ !cast<Operand>("asr_operand_" # ty):$Imm6))
)],
NoItinerary>;
}
: InstAlias<!strconcat(asmop, " $Rn, $Rm"),
(!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
- def : Pat<(opfrag GPR:$Rn, GPR:$Rm),
- (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
+ def : Pat<(opfrag ty:$Rn, ty:$Rm),
+ (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
}
-defm CMPww : cmp_shifts<"CMPww", 0b0, 0b1, 0b0, "cmp", A64cmp, "i32", GPR32>;
-defm CMPxx : cmp_shifts<"CMPxx", 0b1, 0b1, 0b0, "cmp", A64cmp, "i64", GPR64>;
+defm CMPww : cmp_shifts<"CMPww", 0b0, 0b1, 0b0, "cmp", A64cmp, i32, GPR32>;
+defm CMPxx : cmp_shifts<"CMPxx", 0b1, 0b1, 0b0, "cmp", A64cmp, i64, GPR64>;
-defm CMNww : cmp_shifts<"CMNww", 0b0, 0b0, 0b1, "cmn", A64cmn, "i32", GPR32>;
-defm CMNxx : cmp_shifts<"CMNxx", 0b1, 0b0, 0b1, "cmn", A64cmn, "i64", GPR64>;
+defm CMNww : cmp_shifts<"CMNww", 0b0, 0b0, 0b1, "cmn", A64cmn, i32, GPR32>;
+defm CMNxx : cmp_shifts<"CMNxx", 0b1, 0b0, 0b1, "cmn", A64cmn, i64, GPR64>;
//===----------------------------------------------------------------------===//
// Add-subtract (with carry) instructions
//===----------------------------------------------------------------------===//
// Contains: ADC, ADCS, SBC, SBCS + aliases NGC, NGCS
-multiclass A64I_addsubcarrySizes<bit op, bit s, string asmop>
-{
- let Uses = [NZCV] in
- {
+multiclass A64I_addsubcarrySizes<bit op, bit s, string asmop> {
+ let Uses = [NZCV] in {
def www : A64I_addsubcarry<0b0, op, s, 0b000000,
(outs GPR32:$Rd), (ins GPR32:$Rn, GPR32:$Rm),
!strconcat(asmop, "\t$Rd, $Rn, $Rm"),
}
}
-let isCommutable = 1 in
-{
+let isCommutable = 1 in {
defm ADC : A64I_addsubcarrySizes<0b0, 0b0, "adc">;
}
defm SBC : A64I_addsubcarrySizes<0b1, 0b0, "sbc">;
-let Defs = [NZCV] in
-{
- let isCommutable = 1 in
- {
+let Defs = [NZCV] in {
+ let isCommutable = 1 in {
defm ADCS : A64I_addsubcarrySizes<0b0, 0b1, "adcs">;
}
// Note that adde and sube can form a chain longer than two (e.g. for 256-bit
// addition). So the flag-setting instructions are appropriate.
-def : Pat<(adde GPR32:$Rn, GPR32:$Rm), (ADCSwww GPR32:$Rn, GPR32:$Rm)>;
-def : Pat<(adde GPR64:$Rn, GPR64:$Rm), (ADCSxxx GPR64:$Rn, GPR64:$Rm)>;
-def : Pat<(sube GPR32:$Rn, GPR32:$Rm), (SBCSwww GPR32:$Rn, GPR32:$Rm)>;
-def : Pat<(sube GPR64:$Rn, GPR64:$Rm), (SBCSxxx GPR64:$Rn, GPR64:$Rm)>;
+def : Pat<(adde i32:$Rn, i32:$Rm), (ADCSwww $Rn, $Rm)>;
+def : Pat<(adde i64:$Rn, i64:$Rm), (ADCSxxx $Rn, $Rm)>;
+def : Pat<(sube i32:$Rn, i32:$Rm), (SBCSwww $Rn, $Rm)>;
+def : Pat<(sube i64:$Rn, i64:$Rm), (SBCSxxx $Rn, $Rm)>;
//===----------------------------------------------------------------------===//
// Bitfield
// 1. The architectural BFM instructions
//===-------------------------------
-def uimm5_asmoperand : AsmOperandClass
-{
+def uimm5_asmoperand : AsmOperandClass {
let Name = "UImm5";
let PredicateMethod = "isUImm<5>";
let RenderMethod = "addImmOperands";
+ let DiagnosticType = "UImm5";
}
-def uimm6_asmoperand : AsmOperandClass
-{
+def uimm6_asmoperand : AsmOperandClass {
let Name = "UImm6";
let PredicateMethod = "isUImm<6>";
let RenderMethod = "addImmOperands";
+ let DiagnosticType = "UImm6";
}
def bitfield32_imm : Operand<i64>,
- ImmLeaf<i64, [{ return Imm >= 0 && Imm < 32; }]>
-{
+ ImmLeaf<i64, [{ return Imm >= 0 && Imm < 32; }]> {
let ParserMatchClass = uimm5_asmoperand;
let DecoderMethod = "DecodeBitfield32ImmOperand";
def bitfield64_imm : Operand<i64>,
- ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]>
-{
+ ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> {
let ParserMatchClass = uimm6_asmoperand;
// Default decoder works in 64-bit case: the 6-bit field can take any value.
}
-multiclass A64I_bitfieldSizes<bits<2> opc, string asmop>
-{
+multiclass A64I_bitfieldSizes<bits<2> opc, string asmop> {
def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
(ins GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
!strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
- [], NoItinerary>
- {
+ [], NoItinerary> {
let DecoderMethod = "DecodeBitfieldInstruction";
}
def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
(ins GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
!strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
- [], NoItinerary>
- {
+ [], NoItinerary> {
let DecoderMethod = "DecodeBitfieldInstruction";
}
}
def BFMwwii :
A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
(ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
- "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>
-{
+ "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
let DecoderMethod = "DecodeBitfieldInstruction";
let Constraints = "$src = $Rd";
}
def BFMxxii :
A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
(ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
- "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>
-{
+ "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
let DecoderMethod = "DecodeBitfieldInstruction";
let Constraints = "$src = $Rd";
}
// Note that these instructions are strictly more specific than the
// BFM ones (in ImmR) so they can handle their own decoding.
-class A64I_bf_ext<bit sf, bits<2> opc, RegisterClass GPRDest, string asmop,
- bits<6> imms, dag pattern>
+class A64I_bf_ext<bit sf, bits<2> opc, RegisterClass GPRDest, ValueType dty,
+ string asmop, bits<6> imms, dag pattern>
: A64I_bitfield<sf, opc, sf,
(outs GPRDest:$Rd), (ins GPR32:$Rn),
!strconcat(asmop, "\t$Rd, $Rn"),
- [(set GPRDest:$Rd, pattern)], NoItinerary>
-{
+ [(set dty:$Rd, pattern)], NoItinerary> {
let ImmR = 0b000000;
let ImmS = imms;
}
// Signed extensions
-def SXTBxw : A64I_bf_ext<0b1, 0b00, GPR64, "sxtb", 7,
- (sext_inreg (anyext GPR32:$Rn), i8)>;
-def SXTBww : A64I_bf_ext<0b0, 0b00, GPR32, "sxtb", 7,
- (sext_inreg GPR32:$Rn, i8)>;
-def SXTHxw : A64I_bf_ext<0b1, 0b00, GPR64, "sxth", 15,
- (sext_inreg (anyext GPR32:$Rn), i16)>;
-def SXTHww : A64I_bf_ext<0b0, 0b00, GPR32, "sxth", 15,
- (sext_inreg GPR32:$Rn, i16)>;
-def SXTWxw : A64I_bf_ext<0b1, 0b00, GPR64, "sxtw", 31, (sext GPR32:$Rn)>;
+def SXTBxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxtb", 7,
+ (sext_inreg (anyext i32:$Rn), i8)>;
+def SXTBww : A64I_bf_ext<0b0, 0b00, GPR32, i32, "sxtb", 7,
+ (sext_inreg i32:$Rn, i8)>;
+def SXTHxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxth", 15,
+ (sext_inreg (anyext i32:$Rn), i16)>;
+def SXTHww : A64I_bf_ext<0b0, 0b00, GPR32, i32, "sxth", 15,
+ (sext_inreg i32:$Rn, i16)>;
+def SXTWxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxtw", 31, (sext i32:$Rn)>;
// Unsigned extensions
-def UXTBww : A64I_bf_ext<0b0, 0b10, GPR32, "uxtb", 7,
- (and GPR32:$Rn, 255)>;
-def UXTHww : A64I_bf_ext<0b0, 0b10, GPR32, "uxth", 15,
- (and GPR32:$Rn, 65535)>;
+def UXTBww : A64I_bf_ext<0b0, 0b10, GPR32, i32, "uxtb", 7,
+ (and i32:$Rn, 255)>;
+def UXTHww : A64I_bf_ext<0b0, 0b10, GPR32, i32, "uxth", 15,
+ (and i32:$Rn, 65535)>;
// The 64-bit unsigned variants are not strictly architectural but recommended
// for consistency.
-let isAsmParserOnly = 1 in
-{
- def UXTBxw : A64I_bf_ext<0b0, 0b10, GPR64, "uxtb", 7,
- (and (anyext GPR32:$Rn), 255)>;
- def UXTHxw : A64I_bf_ext<0b0, 0b10, GPR64, "uxth", 15,
- (and (anyext GPR32:$Rn), 65535)>;
+let isAsmParserOnly = 1 in {
+ def UXTBxw : A64I_bf_ext<0b0, 0b10, GPR64, i64, "uxtb", 7,
+ (and (anyext i32:$Rn), 255)>;
+ def UXTHxw : A64I_bf_ext<0b0, 0b10, GPR64, i64, "uxth", 15,
+ (and (anyext i32:$Rn), 65535)>;
}
// Extra patterns for when the source register is actually 64-bits
// too. There's no architectural difference here, it's just LLVM
// shinanigans. There's no need for equivalent zero-extension patterns
// because they'll already be caught by logical (immediate) matching.
-def : Pat<(sext_inreg GPR64:$Rn, i8),
- (SXTBxw (EXTRACT_SUBREG GPR64:$Rn, sub_32))>;
-def : Pat<(sext_inreg GPR64:$Rn, i16),
- (SXTHxw (EXTRACT_SUBREG GPR64:$Rn, sub_32))>;
-def : Pat<(sext_inreg GPR64:$Rn, i32),
- (SXTWxw (EXTRACT_SUBREG GPR64:$Rn, sub_32))>;
+def : Pat<(sext_inreg i64:$Rn, i8),
+ (SXTBxw (EXTRACT_SUBREG $Rn, sub_32))>;
+def : Pat<(sext_inreg i64:$Rn, i16),
+ (SXTHxw (EXTRACT_SUBREG $Rn, sub_32))>;
+def : Pat<(sext_inreg i64:$Rn, i32),
+ (SXTWxw (EXTRACT_SUBREG $Rn, sub_32))>;
//===-------------------------------
// These also handle their own decoding because ImmS being set makes
// them take precedence over BFM.
-multiclass A64I_shift<bits<2> opc, string asmop, SDNode opnode>
-{
+multiclass A64I_shift<bits<2> opc, string asmop, SDNode opnode> {
def wwi : A64I_bitfield<0b0, opc, 0b0,
(outs GPR32:$Rd), (ins GPR32:$Rn, bitfield32_imm:$ImmR),
!strconcat(asmop, "\t$Rd, $Rn, $ImmR"),
- [(set GPR32:$Rd, (opnode GPR32:$Rn, bitfield32_imm:$ImmR))],
- NoItinerary>
- {
+ [(set i32:$Rd, (opnode i32:$Rn, bitfield32_imm:$ImmR))],
+ NoItinerary> {
let ImmS = 31;
}
def xxi : A64I_bitfield<0b1, opc, 0b1,
(outs GPR64:$Rd), (ins GPR64:$Rn, bitfield64_imm:$ImmR),
!strconcat(asmop, "\t$Rd, $Rn, $ImmR"),
- [(set GPR64:$Rd, (opnode GPR64:$Rn, bitfield64_imm:$ImmR))],
- NoItinerary>
- {
+ [(set i64:$Rd, (opnode i64:$Rn, bitfield64_imm:$ImmR))],
+ NoItinerary> {
let ImmS = 63;
}
// outweighed the benefits in this case (custom asmparser, printer and selection
// vs custom encoder).
def bitfield32_lsl_imm : Operand<i64>,
- ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]>
-{
+ ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
let ParserMatchClass = uimm5_asmoperand;
let EncoderMethod = "getBitfield32LSLOpValue";
}
def bitfield64_lsl_imm : Operand<i64>,
- ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]>
-{
+ ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
let ParserMatchClass = uimm6_asmoperand;
let EncoderMethod = "getBitfield64LSLOpValue";
}
-class A64I_bitfield_lsl<bit sf, RegisterClass GPR, Operand operand>
+class A64I_bitfield_lsl<bit sf, RegisterClass GPR, ValueType ty,
+ Operand operand>
: A64I_bitfield<sf, 0b10, sf, (outs GPR:$Rd), (ins GPR:$Rn, operand:$FullImm),
"lsl\t$Rd, $Rn, $FullImm",
- [(set GPR:$Rd, (shl GPR:$Rn, operand:$FullImm))],
- NoItinerary>
-{
+ [(set ty:$Rd, (shl ty:$Rn, operand:$FullImm))],
+ NoItinerary> {
bits<12> FullImm;
let ImmR = FullImm{5-0};
let ImmS = FullImm{11-6};
let isAsmParserOnly = 1;
}
-def LSLwwi : A64I_bitfield_lsl<0b0, GPR32, bitfield32_lsl_imm>;
-def LSLxxi : A64I_bitfield_lsl<0b1, GPR64, bitfield64_lsl_imm>;
+def LSLwwi : A64I_bitfield_lsl<0b0, GPR32, i32, bitfield32_lsl_imm>;
+def LSLxxi : A64I_bitfield_lsl<0b1, GPR64, i64, bitfield64_lsl_imm>;
//===-------------------------------
// 5. Aliases for bitfield extract instructions
//===-------------------------------
-def bfx32_width_asmoperand : AsmOperandClass
-{
+def bfx32_width_asmoperand : AsmOperandClass {
let Name = "BFX32Width";
let PredicateMethod = "isBitfieldWidth<32>";
let RenderMethod = "addBFXWidthOperands";
+ let DiagnosticType = "Width32";
}
-def bfx32_width : Operand<i64>, ImmLeaf<i64, [{ return true; }]>
-{
+def bfx32_width : Operand<i64>, ImmLeaf<i64, [{ return true; }]> {
let PrintMethod = "printBFXWidthOperand";
let ParserMatchClass = bfx32_width_asmoperand;
}
-def bfx64_width_asmoperand : AsmOperandClass
-{
+def bfx64_width_asmoperand : AsmOperandClass {
let Name = "BFX64Width";
let PredicateMethod = "isBitfieldWidth<64>";
let RenderMethod = "addBFXWidthOperands";
+ let DiagnosticType = "Width64";
}
-def bfx64_width : Operand<i64>
-{
+def bfx64_width : Operand<i64> {
let PrintMethod = "printBFXWidthOperand";
let ParserMatchClass = bfx64_width_asmoperand;
}
-multiclass A64I_bitfield_extract<bits<2> opc, string asmop, SDNode op>
-{
+multiclass A64I_bitfield_extract<bits<2> opc, string asmop, SDNode op> {
def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
(ins GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
!strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
- [(set GPR32:$Rd, (op GPR32:$Rn, imm:$ImmR, imm:$ImmS))],
- NoItinerary>
- {
+ [(set i32:$Rd, (op i32:$Rn, imm:$ImmR, imm:$ImmS))],
+ NoItinerary> {
// As above, no disassembler allowed.
let isAsmParserOnly = 1;
}
def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
(ins GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
!strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
- [(set GPR64:$Rd, (op GPR64:$Rn, imm:$ImmR, imm:$ImmS))],
- NoItinerary>
- {
+ [(set i64:$Rd, (op i64:$Rn, imm:$ImmR, imm:$ImmS))],
+ NoItinerary> {
// As above, no disassembler allowed.
let isAsmParserOnly = 1;
}
// Again, variants based on BFM modify Rd so need it as an input too.
def BFXILwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
(ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
- "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>
-{
+ "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
// As above, no disassembler allowed.
let isAsmParserOnly = 1;
let Constraints = "$src = $Rd";
def BFXILxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
(ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
- "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>
-{
+ "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
// As above, no disassembler allowed.
let isAsmParserOnly = 1;
let Constraints = "$src = $Rd";
}
// SBFX instructions can do a 1-instruction sign-extension of boolean values.
-def : Pat<(sext_inreg GPR64:$Rn, i1), (SBFXxxii GPR64:$Rn, 0, 0)>;
-def : Pat<(sext_inreg GPR32:$Rn, i1), (SBFXwwii GPR32:$Rn, 0, 0)>;
-def : Pat<(i64 (sext_inreg (anyext GPR32:$Rn), i1)),
- (SBFXxxii (SUBREG_TO_REG (i64 0), GPR32:$Rn, sub_32), 0, 0)>;
+def : Pat<(sext_inreg i64:$Rn, i1), (SBFXxxii $Rn, 0, 0)>;
+def : Pat<(sext_inreg i32:$Rn, i1), (SBFXwwii $Rn, 0, 0)>;
+def : Pat<(i64 (sext_inreg (anyext i32:$Rn), i1)),
+ (SBFXxxii (SUBREG_TO_REG (i64 0), $Rn, sub_32), 0, 0)>;
// UBFX makes sense as an implementation of a 64-bit zero-extension too. Could
// use either 64-bit or 32-bit variant, but 32-bit might be more efficient.
-def : Pat<(zext GPR32:$Rn), (SUBREG_TO_REG (i64 0), (UBFXwwii GPR32:$Rn, 0, 31), sub_32)>;
+def : Pat<(zext i32:$Rn), (SUBREG_TO_REG (i64 0), (UBFXwwii $Rn, 0, 31),
+ sub_32)>;
//===-------------------------------
// 6. Aliases for bitfield insert instructions
//===-------------------------------
-def bfi32_lsb_asmoperand : AsmOperandClass
-{
+def bfi32_lsb_asmoperand : AsmOperandClass {
let Name = "BFI32LSB";
let PredicateMethod = "isUImm<5>";
let RenderMethod = "addBFILSBOperands<32>";
+ let DiagnosticType = "UImm5";
}
-def bfi32_lsb : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]>
-{
+def bfi32_lsb : Operand<i64>,
+ ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
let PrintMethod = "printBFILSBOperand<32>";
let ParserMatchClass = bfi32_lsb_asmoperand;
}
-def bfi64_lsb_asmoperand : AsmOperandClass
-{
+def bfi64_lsb_asmoperand : AsmOperandClass {
let Name = "BFI64LSB";
let PredicateMethod = "isUImm<6>";
let RenderMethod = "addBFILSBOperands<64>";
+ let DiagnosticType = "UImm6";
}
-def bfi64_lsb : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]>
-{
+def bfi64_lsb : Operand<i64>,
+ ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
let PrintMethod = "printBFILSBOperand<64>";
let ParserMatchClass = bfi64_lsb_asmoperand;
}
// Width verification is performed during conversion so width operand can be
// shared between 32/64-bit cases. Still needed for the print method though
// because ImmR encodes "width - 1".
-def bfi32_width_asmoperand : AsmOperandClass
-{
+def bfi32_width_asmoperand : AsmOperandClass {
let Name = "BFI32Width";
let PredicateMethod = "isBitfieldWidth<32>";
let RenderMethod = "addBFIWidthOperands";
+ let DiagnosticType = "Width32";
}
def bfi32_width : Operand<i64>,
- ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 32; }]>
-{
+ ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 32; }]> {
let PrintMethod = "printBFIWidthOperand";
let ParserMatchClass = bfi32_width_asmoperand;
}
-def bfi64_width_asmoperand : AsmOperandClass
-{
+def bfi64_width_asmoperand : AsmOperandClass {
let Name = "BFI64Width";
let PredicateMethod = "isBitfieldWidth<64>";
let RenderMethod = "addBFIWidthOperands";
+ let DiagnosticType = "Width64";
}
def bfi64_width : Operand<i64>,
- ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 64; }]>
-{
+ ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 64; }]> {
let PrintMethod = "printBFIWidthOperand";
let ParserMatchClass = bfi64_width_asmoperand;
}
-multiclass A64I_bitfield_insert<bits<2> opc, string asmop>
-{
+multiclass A64I_bitfield_insert<bits<2> opc, string asmop> {
def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
(ins GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
!strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
- [], NoItinerary>
- {
+ [], NoItinerary> {
// As above, no disassembler allowed.
let isAsmParserOnly = 1;
}
def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
(ins GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
!strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
- [], NoItinerary>
- {
+ [], NoItinerary> {
// As above, no disassembler allowed.
let isAsmParserOnly = 1;
}
-
}
defm SBFIZ : A64I_bitfield_insert<0b00, "sbfiz">;
def BFIwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
- (ins GPR32:$src, GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
- "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>
-{
+ (ins GPR32:$src, GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
+ "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
// As above, no disassembler allowed.
let isAsmParserOnly = 1;
let Constraints = "$src = $Rd";
}
def BFIxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
- (ins GPR64:$src, GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
- "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>
-{
+ (ins GPR64:$src, GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
+ "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
// As above, no disassembler allowed.
let isAsmParserOnly = 1;
let Constraints = "$src = $Rd";
//===----------------------------------------------------------------------===//
// Contains: CBZ, CBNZ
-class label_asmoperand<int width, int scale> : AsmOperandClass
-{
+class label_asmoperand<int width, int scale> : AsmOperandClass {
let Name = "Label" # width # "_" # scale;
let PredicateMethod = "isLabel<" # width # "," # scale # ">";
let RenderMethod = "addLabelOperands<" # width # ", " # scale # ">";
+ let DiagnosticType = "Label";
}
def label_wid19_scal4_asmoperand : label_asmoperand<19, 4>;
// All conditional immediate branches are the same really: 19 signed bits scaled
// by the instruction-size (4).
-def bcc_target : Operand<OtherVT>
-{
+def bcc_target : Operand<OtherVT> {
// This label is a 19-bit offset from PC, scaled by the instruction-width: 4.
let ParserMatchClass = label_wid19_scal4_asmoperand;
let PrintMethod = "printLabelOperand<19, 4>";
let OperandType = "OPERAND_PCREL";
}
-multiclass cmpbr_sizes<bit op, string asmop, ImmLeaf SETOP>
-{
+multiclass cmpbr_sizes<bit op, string asmop, ImmLeaf SETOP> {
let isBranch = 1, isTerminator = 1 in {
def x : A64I_cmpbr<0b1, op,
(outs),
(ins GPR64:$Rt, bcc_target:$Label),
!strconcat(asmop,"\t$Rt, $Label"),
- [(A64br_cc (A64cmp GPR64:$Rt, 0), SETOP, bb:$Label)],
+ [(A64br_cc (A64cmp i64:$Rt, 0), SETOP, bb:$Label)],
NoItinerary>;
def w : A64I_cmpbr<0b0, op,
(outs),
(ins GPR32:$Rt, bcc_target:$Label),
!strconcat(asmop,"\t$Rt, $Label"),
- [(A64br_cc (A64cmp GPR32:$Rt, 0), SETOP, bb:$Label)],
+ [(A64br_cc (A64cmp i32:$Rt, 0), SETOP, bb:$Label)],
NoItinerary>;
}
}
//===----------------------------------------------------------------------===//
// Contains: B.cc
-def cond_code_asmoperand : AsmOperandClass
-{
+def cond_code_asmoperand : AsmOperandClass {
let Name = "CondCode";
+ let DiagnosticType = "CondCode";
}
def cond_code : Operand<i32>, ImmLeaf<i32, [{
return Imm >= 0 && Imm <= 15;
-}]>
-{
+}]> {
let PrintMethod = "printCondCodeOperand";
let ParserMatchClass = cond_code_asmoperand;
}
def Bcc : A64I_condbr<0b0, 0b0, (outs),
(ins cond_code:$Cond, bcc_target:$Label),
"b.$Cond $Label", [(A64br_cc NZCV, (i32 imm:$Cond), bb:$Label)],
- NoItinerary>
-{
+ NoItinerary> {
let Uses = [NZCV];
let isBranch = 1;
let isTerminator = 1;
//===----------------------------------------------------------------------===//
// Contains: CCMN, CCMP
-def uimm4_asmoperand : AsmOperandClass
-{
+def uimm4_asmoperand : AsmOperandClass {
let Name = "UImm4";
let PredicateMethod = "isUImm<4>";
let RenderMethod = "addImmOperands";
+ let DiagnosticType = "UImm4";
}
-def uimm4 : Operand<i32>
-{
+def uimm4 : Operand<i32> {
let ParserMatchClass = uimm4_asmoperand;
}
-def uimm5 : Operand<i32>
-{
+def uimm5 : Operand<i32> {
let ParserMatchClass = uimm5_asmoperand;
}
// The only difference between this operand and the one for instructions like
// B.cc is that it's parsed manually. The other get parsed implicitly as part of
// the mnemonic handling.
-def cond_code_op_asmoperand : AsmOperandClass
-{
+def cond_code_op_asmoperand : AsmOperandClass {
let Name = "CondCodeOp";
let RenderMethod = "addCondCodeOperands";
let PredicateMethod = "isCondCode";
let ParserMethod = "ParseCondCodeOperand";
+ let DiagnosticType = "CondCode";
}
-def cond_code_op : Operand<i32>
-{
+def cond_code_op : Operand<i32> {
let PrintMethod = "printCondCodeOperand";
let ParserMatchClass = cond_code_op_asmoperand;
}
: A64I_condcmpimm<sf, op, 0b0, 0b0, 0b1, (outs),
(ins GPR:$Rn, uimm5:$UImm5, uimm4:$NZCVImm, cond_code_op:$Cond),
!strconcat(asmop, "\t$Rn, $UImm5, $NZCVImm, $Cond"),
- [], NoItinerary>
-{
+ [], NoItinerary> {
let Defs = [NZCV];
}
(outs),
(ins GPR:$Rn, GPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond),
!strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"),
- [], NoItinerary>
-{
+ [], NoItinerary> {
let Defs = [NZCV];
}
// Condition code which is encoded as the inversion (semantically rather than
// bitwise) in the instruction.
-def inv_cond_code_op_asmoperand : AsmOperandClass
-{
+def inv_cond_code_op_asmoperand : AsmOperandClass {
let Name = "InvCondCodeOp";
let RenderMethod = "addInvCondCodeOperands";
let PredicateMethod = "isCondCode";
let ParserMethod = "ParseCondCodeOperand";
+ let DiagnosticType = "CondCode";
}
-def inv_cond_code_op : Operand<i32>
-{
+def inv_cond_code_op : Operand<i32> {
let ParserMatchClass = inv_cond_code_op_asmoperand;
}
multiclass A64I_condselSizes<bit op, bits<2> op2, string asmop,
- SDPatternOperator select>
-{
- let Uses = [NZCV] in
- {
+ SDPatternOperator select> {
+ let Uses = [NZCV] in {
def wwwc : A64I_condsel<0b0, op, 0b0, op2,
(outs GPR32:$Rd),
(ins GPR32:$Rn, GPR32:$Rm, cond_code_op:$Cond),
!strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
- [(set GPR32:$Rd, (select GPR32:$Rn, GPR32:$Rm))],
+ [(set i32:$Rd, (select i32:$Rn, i32:$Rm))],
NoItinerary>;
(outs GPR64:$Rd),
(ins GPR64:$Rn, GPR64:$Rm, cond_code_op:$Cond),
!strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
- [(set GPR64:$Rd, (select GPR64:$Rn, GPR64:$Rm))],
+ [(set i64:$Rd, (select i64:$Rn, i64:$Rm))],
NoItinerary>;
}
}
// No commutable pattern for CSEL since the commuted version is isomorphic.
// CSINC
-def :Pat<(A64select_cc NZCV, (add GPR32:$Rm, 1), GPR32:$Rn, inv_cond_code:$Cond),
- (CSINCwwwc GPR32:$Rn, GPR32:$Rm, inv_cond_code:$Cond)>;
-def :Pat<(A64select_cc NZCV, (add GPR64:$Rm, 1), GPR64:$Rn, inv_cond_code:$Cond),
- (CSINCxxxc GPR64:$Rn, GPR64:$Rm, inv_cond_code:$Cond)>;
+def :Pat<(A64select_cc NZCV, (add i32:$Rm, 1), i32:$Rn, inv_cond_code:$Cond),
+ (CSINCwwwc $Rn, $Rm, inv_cond_code:$Cond)>;
+def :Pat<(A64select_cc NZCV, (add i64:$Rm, 1), i64:$Rn, inv_cond_code:$Cond),
+ (CSINCxxxc $Rn, $Rm, inv_cond_code:$Cond)>;
// CSINV
-def :Pat<(A64select_cc NZCV, (not GPR32:$Rm), GPR32:$Rn, inv_cond_code:$Cond),
- (CSINVwwwc GPR32:$Rn, GPR32:$Rm, inv_cond_code:$Cond)>;
-def :Pat<(A64select_cc NZCV, (not GPR64:$Rm), GPR64:$Rn, inv_cond_code:$Cond),
- (CSINVxxxc GPR64:$Rn, GPR64:$Rm, inv_cond_code:$Cond)>;
+def :Pat<(A64select_cc NZCV, (not i32:$Rm), i32:$Rn, inv_cond_code:$Cond),
+ (CSINVwwwc $Rn, $Rm, inv_cond_code:$Cond)>;
+def :Pat<(A64select_cc NZCV, (not i64:$Rm), i64:$Rn, inv_cond_code:$Cond),
+ (CSINVxxxc $Rn, $Rm, inv_cond_code:$Cond)>;
// CSNEG
-def :Pat<(A64select_cc NZCV, (ineg GPR32:$Rm), GPR32:$Rn, inv_cond_code:$Cond),
- (CSNEGwwwc GPR32:$Rn, GPR32:$Rm, inv_cond_code:$Cond)>;
-def :Pat<(A64select_cc NZCV, (ineg GPR64:$Rm), GPR64:$Rn, inv_cond_code:$Cond),
- (CSNEGxxxc GPR64:$Rn, GPR64:$Rm, inv_cond_code:$Cond)>;
+def :Pat<(A64select_cc NZCV, (ineg i32:$Rm), i32:$Rn, inv_cond_code:$Cond),
+ (CSNEGwwwc $Rn, $Rm, inv_cond_code:$Cond)>;
+def :Pat<(A64select_cc NZCV, (ineg i64:$Rm), i64:$Rn, inv_cond_code:$Cond),
+ (CSNEGxxxc $Rn, $Rm, inv_cond_code:$Cond)>;
//===----------------------------------------------------------------------===//
// Data Processing (1 source) instructions
itin>;
multiclass A64I_dp_1src <bits<6> opcode, string asmop> {
- let neverHasSideEffects = 1 in {
+ let hasSideEffects = 0 in {
def ww : A64I_dp_1src_impl<0b0, opcode, asmop, [], GPR32, NoItinerary>;
def xx : A64I_dp_1src_impl<0b1, opcode, asmop, [], GPR64, NoItinerary>;
}
defm CLS : A64I_dp_1src<0b000101, "cls">;
defm CLZ : A64I_dp_1src<0b000100, "clz">;
-def : Pat<(ctlz GPR32:$Rn), (CLZww GPR32:$Rn)>;
-def : Pat<(ctlz GPR64:$Rn), (CLZxx GPR64:$Rn)>;
-def : Pat<(ctlz_zero_undef GPR32:$Rn), (CLZww GPR32:$Rn)>;
-def : Pat<(ctlz_zero_undef GPR64:$Rn), (CLZxx GPR64:$Rn)>;
+def : Pat<(ctlz i32:$Rn), (CLZww $Rn)>;
+def : Pat<(ctlz i64:$Rn), (CLZxx $Rn)>;
+def : Pat<(ctlz_zero_undef i32:$Rn), (CLZww $Rn)>;
+def : Pat<(ctlz_zero_undef i64:$Rn), (CLZxx $Rn)>;
-def : Pat<(cttz GPR32:$Rn), (CLZww (RBITww GPR32:$Rn))>;
-def : Pat<(cttz GPR64:$Rn), (CLZxx (RBITxx GPR64:$Rn))>;
-def : Pat<(cttz_zero_undef GPR32:$Rn), (CLZww (RBITww GPR32:$Rn))>;
-def : Pat<(cttz_zero_undef GPR64:$Rn), (CLZxx (RBITxx GPR64:$Rn))>;
+def : Pat<(cttz i32:$Rn), (CLZww (RBITww $Rn))>;
+def : Pat<(cttz i64:$Rn), (CLZxx (RBITxx $Rn))>;
+def : Pat<(cttz_zero_undef i32:$Rn), (CLZww (RBITww $Rn))>;
+def : Pat<(cttz_zero_undef i64:$Rn), (CLZxx (RBITxx $Rn))>;
def REVww : A64I_dp_1src_impl<0b0, 0b000010, "rev",
- [(set GPR32:$Rd, (bswap GPR32:$Rn))],
+ [(set i32:$Rd, (bswap i32:$Rn))],
GPR32, NoItinerary>;
def REVxx : A64I_dp_1src_impl<0b1, 0b000011, "rev",
- [(set GPR64:$Rd, (bswap GPR64:$Rn))],
+ [(set i64:$Rd, (bswap i64:$Rn))],
GPR64, NoItinerary>;
def REV32xx : A64I_dp_1src_impl<0b1, 0b000010, "rev32",
- [(set GPR64:$Rd, (bswap (rotr GPR64:$Rn, (i64 32))))],
+ [(set i64:$Rd, (bswap (rotr i64:$Rn, (i64 32))))],
GPR64, NoItinerary>;
def REV16ww : A64I_dp_1src_impl<0b0, 0b000001, "rev16",
- [(set GPR32:$Rd, (bswap (rotr GPR32:$Rn, (i64 16))))],
+ [(set i32:$Rd, (bswap (rotr i32:$Rn, (i64 16))))],
GPR32,
NoItinerary>;
def REV16xx : A64I_dp_1src_impl<0b1, 0b000001, "rev16", [], GPR64, NoItinerary>;
//===----------------------------------------------------------------------===//
// Data Processing (2 sources) instructions
//===----------------------------------------------------------------------===//
-// Contains: UDIV, SDIV, LSLV, LSRV, ASRV, RORV + aliases LSL, LSR, ASR, ROR
+// Contains: CRC32C?[BHWX], UDIV, SDIV, LSLV, LSRV, ASRV, RORV + aliases LSL,
+// LSR, ASR, ROR
+
class dp_2src_impl<bit sf, bits<6> opcode, string asmop, list<dag> patterns,
RegisterClass GPRsp,
patterns,
itin>;
+multiclass dp_2src_crc<bit c, string asmop> {
+ def B_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 0},
+ !strconcat(asmop, "b"), [], GPR32, NoItinerary>;
+ def H_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 1},
+ !strconcat(asmop, "h"), [], GPR32, NoItinerary>;
+ def W_www : dp_2src_impl<0b0, {0, 1, 0, c, 1, 0},
+ !strconcat(asmop, "w"), [], GPR32, NoItinerary>;
+ def X_wwx : A64I_dp_2src<0b1, {0, 1, 0, c, 1, 1}, 0b0,
+ !strconcat(asmop, "x\t$Rd, $Rn, $Rm"),
+ (outs GPR32:$Rd), (ins GPR32:$Rn, GPR64:$Rm), [],
+ NoItinerary>;
+}
+
multiclass dp_2src_zext <bits<6> opcode, string asmop, SDPatternOperator op> {
def www : dp_2src_impl<0b0,
opcode,
asmop,
- [(set GPR32:$Rd, (op GPR32:$Rn, (i64 (zext GPR32:$Rm))))],
+ [(set i32:$Rd,
+ (op i32:$Rn, (i64 (zext i32:$Rm))))],
GPR32,
NoItinerary>;
def xxx : dp_2src_impl<0b1,
opcode,
asmop,
- [(set GPR64:$Rd, (op GPR64:$Rn, GPR64:$Rm))],
+ [(set i64:$Rd, (op i64:$Rn, i64:$Rm))],
GPR64,
NoItinerary>;
}
def www : dp_2src_impl<0b0,
opcode,
asmop,
- [(set GPR32:$Rd, (op GPR32:$Rn, GPR32:$Rm))],
+ [(set i32:$Rd, (op i32:$Rn, i32:$Rm))],
GPR32,
NoItinerary>;
def xxx : dp_2src_impl<0b1,
opcode,
asmop,
- [(set GPR64:$Rd, (op GPR64:$Rn, GPR64:$Rm))],
+ [(set i64:$Rd, (op i64:$Rn, i64:$Rm))],
GPR64,
NoItinerary>;
}
// Here we define the data processing 2 source instructions.
+defm CRC32 : dp_2src_crc<0b0, "crc32">;
+defm CRC32C : dp_2src_crc<0b1, "crc32c">;
+
defm UDIV : dp_2src<0b000010, "udiv", udiv>;
defm SDIV : dp_2src<0b000011, "sdiv", sdiv>;
// operation. Since the LLVM operations are undefined (as in C) if the
// RHS is out of range, it's perfectly permissible to discard the high
// bits of the GPR64.
-def : Pat<(shl GPR32:$Rn, GPR64:$Rm),
- (LSLVwww GPR32:$Rn, (EXTRACT_SUBREG GPR64:$Rm, sub_32))>;
-def : Pat<(srl GPR32:$Rn, GPR64:$Rm),
- (LSRVwww GPR32:$Rn, (EXTRACT_SUBREG GPR64:$Rm, sub_32))>;
-def : Pat<(sra GPR32:$Rn, GPR64:$Rm),
- (ASRVwww GPR32:$Rn, (EXTRACT_SUBREG GPR64:$Rm, sub_32))>;
-def : Pat<(rotr GPR32:$Rn, GPR64:$Rm),
- (RORVwww GPR32:$Rn, (EXTRACT_SUBREG GPR64:$Rm, sub_32))>;
+def : Pat<(shl i32:$Rn, i64:$Rm),
+ (LSLVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
+def : Pat<(srl i32:$Rn, i64:$Rm),
+ (LSRVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
+def : Pat<(sra i32:$Rn, i64:$Rm),
+ (ASRVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
+def : Pat<(rotr i32:$Rn, i64:$Rm),
+ (RORVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
// Here we define the aliases for the data processing 2 source instructions.
def LSL_mnemonic : MnemonicAlias<"lslv", "lsl">;
// + aliases MUL, MNEG, SMULL, SMNEGL, UMULL, UMNEGL
class A64I_dp3_4operand<bit sf, bits<6> opcode, RegisterClass AccReg,
- RegisterClass SrcReg, string asmop, dag pattern>
+ ValueType AccTy, RegisterClass SrcReg,
+ string asmop, dag pattern>
: A64I_dp3<sf, opcode,
(outs AccReg:$Rd), (ins SrcReg:$Rn, SrcReg:$Rm, AccReg:$Ra),
!strconcat(asmop, "\t$Rd, $Rn, $Rm, $Ra"),
- [(set AccReg:$Rd, pattern)], NoItinerary>
-{
+ [(set AccTy:$Rd, pattern)], NoItinerary> {
RegisterClass AccGPR = AccReg;
RegisterClass SrcGPR = SrcReg;
}
-def MADDwwww : A64I_dp3_4operand<0b0, 0b000000, GPR32, GPR32, "madd",
- (add GPR32:$Ra, (mul GPR32:$Rn, GPR32:$Rm))>;
-def MADDxxxx : A64I_dp3_4operand<0b1, 0b000000, GPR64, GPR64, "madd",
- (add GPR64:$Ra, (mul GPR64:$Rn, GPR64:$Rm))>;
+def MADDwwww : A64I_dp3_4operand<0b0, 0b000000, GPR32, i32, GPR32, "madd",
+ (add i32:$Ra, (mul i32:$Rn, i32:$Rm))>;
+def MADDxxxx : A64I_dp3_4operand<0b1, 0b000000, GPR64, i64, GPR64, "madd",
+ (add i64:$Ra, (mul i64:$Rn, i64:$Rm))>;
-def MSUBwwww : A64I_dp3_4operand<0b0, 0b000001, GPR32, GPR32, "msub",
- (sub GPR32:$Ra, (mul GPR32:$Rn, GPR32:$Rm))>;
-def MSUBxxxx : A64I_dp3_4operand<0b1, 0b000001, GPR64, GPR64, "msub",
- (sub GPR64:$Ra, (mul GPR64:$Rn, GPR64:$Rm))>;
+def MSUBwwww : A64I_dp3_4operand<0b0, 0b000001, GPR32, i32, GPR32, "msub",
+ (sub i32:$Ra, (mul i32:$Rn, i32:$Rm))>;
+def MSUBxxxx : A64I_dp3_4operand<0b1, 0b000001, GPR64, i64, GPR64, "msub",
+ (sub i64:$Ra, (mul i64:$Rn, i64:$Rm))>;
-def SMADDLxwwx : A64I_dp3_4operand<0b1, 0b000010, GPR64, GPR32, "smaddl",
- (add GPR64:$Ra, (mul (i64 (sext GPR32:$Rn)), (sext GPR32:$Rm)))>;
-def SMSUBLxwwx : A64I_dp3_4operand<0b1, 0b000011, GPR64, GPR32, "smsubl",
- (sub GPR64:$Ra, (mul (i64 (sext GPR32:$Rn)), (sext GPR32:$Rm)))>;
+def SMADDLxwwx : A64I_dp3_4operand<0b1, 0b000010, GPR64, i64, GPR32, "smaddl",
+ (add i64:$Ra, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>;
+def SMSUBLxwwx : A64I_dp3_4operand<0b1, 0b000011, GPR64, i64, GPR32, "smsubl",
+ (sub i64:$Ra, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>;
-def UMADDLxwwx : A64I_dp3_4operand<0b1, 0b001010, GPR64, GPR32, "umaddl",
- (add GPR64:$Ra, (mul (i64 (zext GPR32:$Rn)), (zext GPR32:$Rm)))>;
-def UMSUBLxwwx : A64I_dp3_4operand<0b1, 0b001011, GPR64, GPR32, "umsubl",
- (sub GPR64:$Ra, (mul (i64 (zext GPR32:$Rn)), (zext GPR32:$Rm)))>;
+def UMADDLxwwx : A64I_dp3_4operand<0b1, 0b001010, GPR64, i64, GPR32, "umaddl",
+ (add i64:$Ra, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>;
+def UMSUBLxwwx : A64I_dp3_4operand<0b1, 0b001011, GPR64, i64, GPR32, "umsubl",
+ (sub i64:$Ra, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>;
-let isCommutable = 1, PostEncoderMethod = "fixMulHigh" in
-{
+let isCommutable = 1, PostEncoderMethod = "fixMulHigh" in {
def UMULHxxx : A64I_dp3<0b1, 0b001100, (outs GPR64:$Rd),
(ins GPR64:$Rn, GPR64:$Rm),
"umulh\t$Rd, $Rn, $Rm",
- [(set GPR64:$Rd, (mulhu GPR64:$Rn, GPR64:$Rm))],
+ [(set i64:$Rd, (mulhu i64:$Rn, i64:$Rm))],
NoItinerary>;
def SMULHxxx : A64I_dp3<0b1, 0b000100, (outs GPR64:$Rd),
(ins GPR64:$Rn, GPR64:$Rm),
"smulh\t$Rd, $Rn, $Rm",
- [(set GPR64:$Rd, (mulhs GPR64:$Rn, GPR64:$Rm))],
+ [(set i64:$Rd, (mulhs i64:$Rn, i64:$Rm))],
NoItinerary>;
}
multiclass A64I_dp3_3operand<string asmop, A64I_dp3_4operand INST,
- Register ZR, dag pattern>
-{
+ Register ZR, dag pattern> {
def : InstAlias<asmop # " $Rd, $Rn, $Rm",
(INST INST.AccGPR:$Rd, INST.SrcGPR:$Rn, INST.SrcGPR:$Rm, ZR)>;
- def : Pat<pattern, (INST INST.SrcGPR:$Rn, INST.SrcGPR:$Rm, ZR)>;
+ def : Pat<pattern, (INST $Rn, $Rm, ZR)>;
}
-defm : A64I_dp3_3operand<"mul", MADDwwww, WZR, (mul GPR32:$Rn, GPR32:$Rm)>;
-defm : A64I_dp3_3operand<"mul", MADDxxxx, XZR, (mul GPR64:$Rn, GPR64:$Rm)>;
+defm : A64I_dp3_3operand<"mul", MADDwwww, WZR, (mul i32:$Rn, i32:$Rm)>;
+defm : A64I_dp3_3operand<"mul", MADDxxxx, XZR, (mul i64:$Rn, i64:$Rm)>;
defm : A64I_dp3_3operand<"mneg", MSUBwwww, WZR,
- (sub 0, (mul GPR32:$Rn, GPR32:$Rm))>;
+ (sub 0, (mul i32:$Rn, i32:$Rm))>;
defm : A64I_dp3_3operand<"mneg", MSUBxxxx, XZR,
- (sub 0, (mul GPR64:$Rn, GPR64:$Rm))>;
+ (sub 0, (mul i64:$Rn, i64:$Rm))>;
defm : A64I_dp3_3operand<"smull", SMADDLxwwx, XZR,
- (mul (i64 (sext GPR32:$Rn)), (sext GPR32:$Rm))>;
+ (mul (i64 (sext i32:$Rn)), (sext i32:$Rm))>;
defm : A64I_dp3_3operand<"smnegl", SMSUBLxwwx, XZR,
- (sub 0, (mul (i64 (sext GPR32:$Rn)), (sext GPR32:$Rm)))>;
+ (sub 0, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>;
defm : A64I_dp3_3operand<"umull", UMADDLxwwx, XZR,
- (mul (i64 (zext GPR32:$Rn)), (zext GPR32:$Rm))>;
+ (mul (i64 (zext i32:$Rn)), (zext i32:$Rm))>;
defm : A64I_dp3_3operand<"umnegl", UMSUBLxwwx, XZR,
- (sub 0, (mul (i64 (zext GPR32:$Rn)), (zext GPR32:$Rm)))>;
+ (sub 0, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>;
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Contains: SVC, HVC, SMC, BRK, HLT, DCPS1, DCPS2, DCPS3
-def uimm16_asmoperand : AsmOperandClass
-{
+def uimm16_asmoperand : AsmOperandClass {
let Name = "UImm16";
let PredicateMethod = "isUImm<16>";
let RenderMethod = "addImmOperands";
+ let DiagnosticType = "UImm16";
}
-def uimm16 : Operand<i32>
-{
+def uimm16 : Operand<i32> {
let ParserMatchClass = uimm16_asmoperand;
}
class A64I_exceptImpl<bits<3> opc, bits<2> ll, string asmop>
: A64I_exception<opc, 0b000, ll, (outs), (ins uimm16:$UImm16),
- !strconcat(asmop, "\t$UImm16"), [], NoItinerary>
-{
+ !strconcat(asmop, "\t$UImm16"), [], NoItinerary> {
let isBranch = 1;
let isTerminator = 1;
}
(outs GPR32:$Rd),
(ins GPR32:$Rn, GPR32:$Rm, bitfield32_imm:$LSB),
"extr\t$Rd, $Rn, $Rm, $LSB",
- [(set GPR32:$Rd,
- (A64Extr GPR32:$Rn, GPR32:$Rm, imm:$LSB))],
+ [(set i32:$Rd,
+ (A64Extr i32:$Rn, i32:$Rm, imm:$LSB))],
NoItinerary>;
def EXTRxxxi : A64I_extract<0b1, 0b000, 0b1,
(outs GPR64:$Rd),
(ins GPR64:$Rn, GPR64:$Rm, bitfield64_imm:$LSB),
"extr\t$Rd, $Rn, $Rm, $LSB",
- [(set GPR64:$Rd,
- (A64Extr GPR64:$Rn, GPR64:$Rm, imm:$LSB))],
+ [(set i64:$Rd,
+ (A64Extr i64:$Rn, i64:$Rm, imm:$LSB))],
NoItinerary>;
def : InstAlias<"ror $Rd, $Rs, $LSB",
def : InstAlias<"ror $Rd, $Rs, $LSB",
(EXTRxxxi GPR64:$Rd, GPR64:$Rs, GPR64:$Rs, bitfield64_imm:$LSB)>;
-def : Pat<(rotr GPR32:$Rn, bitfield32_imm:$LSB),
- (EXTRwwwi GPR32:$Rn, GPR32:$Rn, bitfield32_imm:$LSB)>;
-def : Pat<(rotr GPR64:$Rn, bitfield64_imm:$LSB),
- (EXTRxxxi GPR64:$Rn, GPR64:$Rn, bitfield64_imm:$LSB)>;
+def : Pat<(rotr i32:$Rn, bitfield32_imm:$LSB),
+ (EXTRwwwi $Rn, $Rn, bitfield32_imm:$LSB)>;
+def : Pat<(rotr i64:$Rn, bitfield64_imm:$LSB),
+ (EXTRxxxi $Rn, $Rn, bitfield64_imm:$LSB)>;
//===----------------------------------------------------------------------===//
// Floating-point compare instructions
//===----------------------------------------------------------------------===//
// Contains: FCMP, FCMPE
-def fpzero_asmoperand : AsmOperandClass
-{
+def fpzero_asmoperand : AsmOperandClass {
let Name = "FPZero";
let ParserMethod = "ParseFPImmOperand";
+ let DiagnosticType = "FPZero";
}
-def fpz32 : Operand<f32>, ComplexPattern<f32, 1, "SelectFPZeroOperand", [fpimm]>
-{
+def fpz32 : Operand<f32>,
+ ComplexPattern<f32, 1, "SelectFPZeroOperand", [fpimm]> {
let ParserMatchClass = fpzero_asmoperand;
let PrintMethod = "printFPZeroOperand";
+ let DecoderMethod = "DecodeFPZeroOperand";
}
-def fpz64 : Operand<f64>, ComplexPattern<f64, 1, "SelectFPZeroOperand", [fpimm]>
-{
+def fpz64 : Operand<f64>,
+ ComplexPattern<f64, 1, "SelectFPZeroOperand", [fpimm]> {
let ParserMatchClass = fpzero_asmoperand;
let PrintMethod = "printFPZeroOperand";
+ let DecoderMethod = "DecodeFPZeroOperand";
}
-multiclass A64I_fpcmpSignal<bits<2> type, bit imm, dag ins, string asmop2,
- dag pattern>
-{
+def fpz64movi : Operand<i64>,
+ ComplexPattern<f64, 1, "SelectFPZeroOperand", [fpimm]> {
+ let ParserMatchClass = fpzero_asmoperand;
+ let PrintMethod = "printFPZeroOperand";
+ let DecoderMethod = "DecodeFPZeroOperand";
+}
+
+multiclass A64I_fpcmpSignal<bits<2> type, bit imm, dag ins, dag pattern> {
def _quiet : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b0, imm, 0b0, 0b0, 0b0},
- (outs), ins, !strconcat("fcmp\t$Rn, ", asmop2),
- [pattern], NoItinerary>
- {
+ (outs), ins, "fcmp\t$Rn, $Rm", [pattern],
+ NoItinerary> {
let Defs = [NZCV];
}
def _sig : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b1, imm, 0b0, 0b0, 0b0},
- (outs), ins, !strconcat("fcmpe\t$Rn, ", asmop2),
- [], NoItinerary>
- {
+ (outs), ins, "fcmpe\t$Rn, $Rm", [], NoItinerary> {
let Defs = [NZCV];
}
}
-defm FCMPss : A64I_fpcmpSignal<0b00, 0b0, (ins FPR32:$Rn, FPR32:$Rm), "$Rm",
- (set NZCV, (A64cmp (f32 FPR32:$Rn), FPR32:$Rm))>;
-defm FCMPdd : A64I_fpcmpSignal<0b01, 0b0, (ins FPR64:$Rn, FPR64:$Rm), "$Rm",
- (set NZCV, (A64cmp (f64 FPR64:$Rn), FPR64:$Rm))>;
+defm FCMPss : A64I_fpcmpSignal<0b00, 0b0, (ins FPR32:$Rn, FPR32:$Rm),
+ (set NZCV, (A64cmp f32:$Rn, f32:$Rm))>;
+defm FCMPdd : A64I_fpcmpSignal<0b01, 0b0, (ins FPR64:$Rn, FPR64:$Rm),
+ (set NZCV, (A64cmp f64:$Rn, f64:$Rm))>;
-// What would be Rm should be written as 0, but anything is valid for
-// disassembly so we can't set the bits
-let PostEncoderMethod = "fixFCMPImm" in
-{
- defm FCMPsi : A64I_fpcmpSignal<0b00, 0b1, (ins FPR32:$Rn, fpz32:$Imm), "$Imm",
- (set NZCV, (A64cmp (f32 FPR32:$Rn), fpz32:$Imm))>;
+// What would be Rm should be written as 0; note that even though it's called
+// "$Rm" here to fit in with the InstrFormats, it's actually an immediate.
+defm FCMPsi : A64I_fpcmpSignal<0b00, 0b1, (ins FPR32:$Rn, fpz32:$Rm),
+ (set NZCV, (A64cmp f32:$Rn, fpz32:$Rm))>;
- defm FCMPdi : A64I_fpcmpSignal<0b01, 0b1, (ins FPR64:$Rn, fpz64:$Imm), "$Imm",
- (set NZCV, (A64cmp (f64 FPR64:$Rn), fpz64:$Imm))>;
-}
+defm FCMPdi : A64I_fpcmpSignal<0b01, 0b1, (ins FPR64:$Rn, fpz64:$Rm),
+ (set NZCV, (A64cmp f64:$Rn, fpz64:$Rm))>;
//===----------------------------------------------------------------------===//
(outs),
(ins FPR:$Rn, FPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond),
!strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"),
- [], NoItinerary>
-{
+ [], NoItinerary> {
let Defs = [NZCV];
}
//===----------------------------------------------------------------------===//
// Contains: FCSEL
-let Uses = [NZCV] in
-{
+let Uses = [NZCV] in {
def FCSELsssc : A64I_fpcondsel<0b0, 0b0, 0b00, (outs FPR32:$Rd),
(ins FPR32:$Rn, FPR32:$Rm, cond_code_op:$Cond),
"fcsel\t$Rd, $Rn, $Rm, $Cond",
- [(set FPR32:$Rd,
- (simple_select (f32 FPR32:$Rn),
- FPR32:$Rm))],
+ [(set f32:$Rd,
+ (simple_select f32:$Rn, f32:$Rm))],
NoItinerary>;
def FCSELdddc : A64I_fpcondsel<0b0, 0b0, 0b01, (outs FPR64:$Rd),
(ins FPR64:$Rn, FPR64:$Rm, cond_code_op:$Cond),
"fcsel\t$Rd, $Rn, $Rm, $Cond",
- [(set FPR64:$Rd,
- (simple_select (f64 FPR64:$Rn),
- FPR64:$Rm))],
+ [(set f64:$Rd,
+ (simple_select f64:$Rn, f64:$Rm))],
NoItinerary>;
}
// First we do the fairly trivial bunch with uniform "OP s, s" and "OP d, d"
// syntax. Default to no pattern because most are odd enough not to have one.
multiclass A64I_fpdp1sizes<bits<6> opcode, string asmstr,
- SDPatternOperator opnode = FPNoUnop>
-{
+ SDPatternOperator opnode = FPNoUnop> {
def ss : A64I_fpdp1<0b0, 0b0, 0b00, opcode, (outs FPR32:$Rd), (ins FPR32:$Rn),
!strconcat(asmstr, "\t$Rd, $Rn"),
- [(set (f32 FPR32:$Rd), (opnode FPR32:$Rn))],
+ [(set f32:$Rd, (opnode f32:$Rn))],
NoItinerary>;
def dd : A64I_fpdp1<0b0, 0b0, 0b01, opcode, (outs FPR64:$Rd), (ins FPR64:$Rn),
!strconcat(asmstr, "\t$Rd, $Rn"),
- [(set (f64 FPR64:$Rd), (opnode FPR64:$Rn))],
+ [(set f64:$Rd, (opnode f64:$Rn))],
NoItinerary>;
}
// The FCVT instrucitons have different source and destination register-types,
// but the fields are uniform everywhere a D-register (say) crops up. Package
// this information in a Record.
-class FCVTRegType<RegisterClass rc, bits<2> fld, ValueType vt>
-{
+class FCVTRegType<RegisterClass rc, bits<2> fld, ValueType vt> {
RegisterClass Class = rc;
ValueType VT = vt;
bit t1 = fld{1};
{0,0,0,1, DestReg.t1, DestReg.t0},
(outs DestReg.Class:$Rd), (ins SrcReg.Class:$Rn),
"fcvt\t$Rd, $Rn",
- [(set (DestReg.VT DestReg.Class:$Rd),
- (opnode (SrcReg.VT SrcReg.Class:$Rn)))], NoItinerary>;
+ [(set DestReg.VT:$Rd, (opnode SrcReg.VT:$Rn))], NoItinerary>;
def FCVTds : A64I_fpdp1_fcvt<FCVT64, FCVT32, fextend>;
def FCVThs : A64I_fpdp1_fcvt<FCVT16, FCVT32, fround>;
[{ (void)N; return false; }]>;
multiclass A64I_fpdp2sizes<bits<4> opcode, string asmstr,
- SDPatternOperator opnode>
-{
+ SDPatternOperator opnode> {
def sss : A64I_fpdp2<0b0, 0b0, 0b00, opcode,
(outs FPR32:$Rd),
(ins FPR32:$Rn, FPR32:$Rm),
!strconcat(asmstr, "\t$Rd, $Rn, $Rm"),
- [(set (f32 FPR32:$Rd), (opnode FPR32:$Rn, FPR32:$Rm))],
+ [(set f32:$Rd, (opnode f32:$Rn, f32:$Rm))],
NoItinerary>;
def ddd : A64I_fpdp2<0b0, 0b0, 0b01, opcode,
(outs FPR64:$Rd),
(ins FPR64:$Rn, FPR64:$Rm),
!strconcat(asmstr, "\t$Rd, $Rn, $Rm"),
- [(set (f64 FPR64:$Rd), (opnode FPR64:$Rn, FPR64:$Rm))],
+ [(set f64:$Rd, (opnode f64:$Rn, f64:$Rm))],
NoItinerary>;
}
: A64I_fpdp3<0b0, 0b0, type, o1, o0, (outs FPR:$Rd),
(ins FPR:$Rn, FPR:$Rm, FPR:$Ra),
!strconcat(asmop,"\t$Rd, $Rn, $Rm, $Ra"),
- [(set FPR:$Rd, (fmakind (VT FPR:$Rn), FPR:$Rm, FPR:$Ra))],
+ [(set VT:$Rd, (fmakind VT:$Rn, VT:$Rm, VT:$Ra))],
NoItinerary>;
def FMADDssss : A64I_fpdp3Impl<"fmadd", FPR32, f32, 0b00, 0b0, 0b0, fma>;
def FNMADDdddd : A64I_fpdp3Impl<"fnmadd", FPR64, f64, 0b01, 0b1, 0b0, fnmadd>;
def FNMSUBdddd : A64I_fpdp3Impl<"fnmsub", FPR64, f64, 0b01, 0b1, 0b1, fnmsub>;
+// Extra patterns for when we're allowed to optimise separate multiplication and
+// addition.
+let Predicates = [HasFPARMv8, UseFusedMAC] in {
+def : Pat<(f32 (fadd FPR32:$Ra, (f32 (fmul FPR32:$Rn, FPR32:$Rm)))),
+ (FMADDssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
+def : Pat<(f32 (fsub FPR32:$Ra, (f32 (fmul FPR32:$Rn, FPR32:$Rm)))),
+ (FMSUBssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
+def : Pat<(f32 (fsub (f32 (fmul FPR32:$Rn, FPR32:$Rm)), FPR32:$Ra)),
+ (FNMADDssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
+def : Pat<(f32 (fsub (f32 (fneg FPR32:$Ra)), (f32 (fmul FPR32:$Rn, FPR32:$Rm)))),
+ (FNMSUBssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
+
+def : Pat<(f64 (fadd FPR64:$Ra, (f64 (fmul FPR64:$Rn, FPR64:$Rm)))),
+ (FMADDdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
+def : Pat<(f64 (fsub FPR64:$Ra, (f64 (fmul FPR64:$Rn, FPR64:$Rm)))),
+ (FMSUBdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
+def : Pat<(f64 (fsub (f64 (fmul FPR64:$Rn, FPR64:$Rm)), FPR64:$Ra)),
+ (FNMADDdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
+def : Pat<(f64 (fsub (f64 (fneg FPR64:$Ra)), (f64 (fmul FPR64:$Rn, FPR64:$Rm)))),
+ (FNMSUBdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
+}
+
+
//===----------------------------------------------------------------------===//
// Floating-point <-> fixed-point conversion instructions
//===----------------------------------------------------------------------===//
// Contains: FCVTZS, FCVTZU, SCVTF, UCVTF
// #1-#32 allowed, encoded as "64 - <specified imm>
-def fixedpos_asmoperand_i32 : AsmOperandClass
-{
+def fixedpos_asmoperand_i32 : AsmOperandClass {
let Name = "CVTFixedPos32";
let RenderMethod = "addCVTFixedPosOperands";
let PredicateMethod = "isCVTFixedPos<32>";
+ let DiagnosticType = "CVTFixedPos32";
}
// Also encoded as "64 - <specified imm>" but #1-#64 allowed.
-def fixedpos_asmoperand_i64 : AsmOperandClass
-{
+def fixedpos_asmoperand_i64 : AsmOperandClass {
let Name = "CVTFixedPos64";
let RenderMethod = "addCVTFixedPosOperands";
let PredicateMethod = "isCVTFixedPos<64>";
+ let DiagnosticType = "CVTFixedPos64";
}
// We need the cartesian product of f32/f64 i32/i64 operands for
// + Assembly parsing and decoding depend on integer width
class cvtfix_i32_op<ValueType FloatVT>
: Operand<FloatVT>,
- ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm]>
-{
+ ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm]> {
let ParserMatchClass = fixedpos_asmoperand_i32;
let DecoderMethod = "DecodeCVT32FixedPosOperand";
let PrintMethod = "printCVTFixedPosOperand";
class cvtfix_i64_op<ValueType FloatVT>
: Operand<FloatVT>,
- ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm]>
-{
+ ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm]> {
let ParserMatchClass = fixedpos_asmoperand_i64;
let PrintMethod = "printCVTFixedPosOperand";
}
// worth going for a multiclass here. Oh well.
class A64I_fptofix<bit sf, bits<2> type, bits<3> opcode,
- RegisterClass GPR, RegisterClass FPR, Operand scale_op,
- string asmop, SDNode cvtop>
+ RegisterClass GPR, RegisterClass FPR,
+ ValueType DstTy, ValueType SrcTy,
+ Operand scale_op, string asmop, SDNode cvtop>
: A64I_fpfixed<sf, 0b0, type, 0b11, opcode,
(outs GPR:$Rd), (ins FPR:$Rn, scale_op:$Scale),
!strconcat(asmop, "\t$Rd, $Rn, $Scale"),
- [(set GPR:$Rd, (cvtop (fmul FPR:$Rn, scale_op:$Scale)))],
+ [(set DstTy:$Rd, (cvtop (fmul SrcTy:$Rn, scale_op:$Scale)))],
NoItinerary>;
-def FCVTZSwsi : A64I_fptofix<0b0, 0b00, 0b000, GPR32, FPR32,
+def FCVTZSwsi : A64I_fptofix<0b0, 0b00, 0b000, GPR32, FPR32, i32, f32,
cvtfix_i32_op<f32>, "fcvtzs", fp_to_sint>;
-def FCVTZSxsi : A64I_fptofix<0b1, 0b00, 0b000, GPR64, FPR32,
+def FCVTZSxsi : A64I_fptofix<0b1, 0b00, 0b000, GPR64, FPR32, i64, f32,
cvtfix_i64_op<f32>, "fcvtzs", fp_to_sint>;
-def FCVTZUwsi : A64I_fptofix<0b0, 0b00, 0b001, GPR32, FPR32,
+def FCVTZUwsi : A64I_fptofix<0b0, 0b00, 0b001, GPR32, FPR32, i32, f32,
cvtfix_i32_op<f32>, "fcvtzu", fp_to_uint>;
-def FCVTZUxsi : A64I_fptofix<0b1, 0b00, 0b001, GPR64, FPR32,
+def FCVTZUxsi : A64I_fptofix<0b1, 0b00, 0b001, GPR64, FPR32, i64, f32,
cvtfix_i64_op<f32>, "fcvtzu", fp_to_uint>;
-def FCVTZSwdi : A64I_fptofix<0b0, 0b01, 0b000, GPR32, FPR64,
+def FCVTZSwdi : A64I_fptofix<0b0, 0b01, 0b000, GPR32, FPR64, i32, f64,
cvtfix_i32_op<f64>, "fcvtzs", fp_to_sint>;
-def FCVTZSxdi : A64I_fptofix<0b1, 0b01, 0b000, GPR64, FPR64,
+def FCVTZSxdi : A64I_fptofix<0b1, 0b01, 0b000, GPR64, FPR64, i64, f64,
cvtfix_i64_op<f64>, "fcvtzs", fp_to_sint>;
-def FCVTZUwdi : A64I_fptofix<0b0, 0b01, 0b001, GPR32, FPR64,
+def FCVTZUwdi : A64I_fptofix<0b0, 0b01, 0b001, GPR32, FPR64, i32, f64,
cvtfix_i32_op<f64>, "fcvtzu", fp_to_uint>;
-def FCVTZUxdi : A64I_fptofix<0b1, 0b01, 0b001, GPR64, FPR64,
+def FCVTZUxdi : A64I_fptofix<0b1, 0b01, 0b001, GPR64, FPR64, i64, f64,
cvtfix_i64_op<f64>, "fcvtzu", fp_to_uint>;
class A64I_fixtofp<bit sf, bits<2> type, bits<3> opcode,
- RegisterClass FPR, RegisterClass GPR, Operand scale_op,
- string asmop, SDNode cvtop>
+ RegisterClass FPR, RegisterClass GPR,
+ ValueType DstTy, ValueType SrcTy,
+ Operand scale_op, string asmop, SDNode cvtop>
: A64I_fpfixed<sf, 0b0, type, 0b00, opcode,
(outs FPR:$Rd), (ins GPR:$Rn, scale_op:$Scale),
!strconcat(asmop, "\t$Rd, $Rn, $Scale"),
- [(set FPR:$Rd, (fdiv (cvtop GPR:$Rn), scale_op:$Scale))],
+ [(set DstTy:$Rd, (fdiv (cvtop SrcTy:$Rn), scale_op:$Scale))],
NoItinerary>;
-def SCVTFswi : A64I_fixtofp<0b0, 0b00, 0b010, FPR32, GPR32,
+def SCVTFswi : A64I_fixtofp<0b0, 0b00, 0b010, FPR32, GPR32, f32, i32,
cvtfix_i32_op<f32>, "scvtf", sint_to_fp>;
-def SCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b010, FPR32, GPR64,
+def SCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b010, FPR32, GPR64, f32, i64,
cvtfix_i64_op<f32>, "scvtf", sint_to_fp>;
-def UCVTFswi : A64I_fixtofp<0b0, 0b00, 0b011, FPR32, GPR32,
+def UCVTFswi : A64I_fixtofp<0b0, 0b00, 0b011, FPR32, GPR32, f32, i32,
cvtfix_i32_op<f32>, "ucvtf", uint_to_fp>;
-def UCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b011, FPR32, GPR64,
+def UCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b011, FPR32, GPR64, f32, i64,
cvtfix_i64_op<f32>, "ucvtf", uint_to_fp>;
-def SCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b010, FPR64, GPR32,
+def SCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b010, FPR64, GPR32, f64, i32,
cvtfix_i32_op<f64>, "scvtf", sint_to_fp>;
-def SCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b010, FPR64, GPR64,
+def SCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b010, FPR64, GPR64, f64, i64,
cvtfix_i64_op<f64>, "scvtf", sint_to_fp>;
-def UCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b011, FPR64, GPR32,
+def UCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b011, FPR64, GPR32, f64, i32,
cvtfix_i32_op<f64>, "ucvtf", uint_to_fp>;
-def UCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b011, FPR64, GPR64,
+def UCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b011, FPR64, GPR64, f64, i64,
cvtfix_i64_op<f64>, "ucvtf", uint_to_fp>;
//===----------------------------------------------------------------------===//
: A64I_fpint<sf, 0b0, type, rmode, opcode, (outs DestPR:$Rd), (ins SrcPR:$Rn),
!strconcat(asmop, "\t$Rd, $Rn"), [], NoItinerary>;
-multiclass A64I_fptointRM<bits<2> rmode, bit o2, string asmop>
-{
- def Sws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 0}, GPR32, FPR32, asmop # "s">;
- def Sxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 0}, GPR64, FPR32, asmop # "s">;
- def Uws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 1}, GPR32, FPR32, asmop # "u">;
- def Uxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 1}, GPR64, FPR32, asmop # "u">;
-
- def Swd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 0}, GPR32, FPR64, asmop # "s">;
- def Sxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 0}, GPR64, FPR64, asmop # "s">;
- def Uwd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 1}, GPR32, FPR64, asmop # "u">;
- def Uxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 1}, GPR64, FPR64, asmop # "u">;
+multiclass A64I_fptointRM<bits<2> rmode, bit o2, string asmop> {
+ def Sws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 0},
+ GPR32, FPR32, asmop # "s">;
+ def Sxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 0},
+ GPR64, FPR32, asmop # "s">;
+ def Uws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 1},
+ GPR32, FPR32, asmop # "u">;
+ def Uxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 1},
+ GPR64, FPR32, asmop # "u">;
+
+ def Swd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 0},
+ GPR32, FPR64, asmop # "s">;
+ def Sxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 0},
+ GPR64, FPR64, asmop # "s">;
+ def Uwd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 1},
+ GPR32, FPR64, asmop # "u">;
+ def Uxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 1},
+ GPR64, FPR64, asmop # "u">;
}
defm FCVTN : A64I_fptointRM<0b00, 0b0, "fcvtn">;
defm FCVTZ : A64I_fptointRM<0b11, 0b0, "fcvtz">;
defm FCVTA : A64I_fptointRM<0b00, 0b1, "fcvta">;
-def : Pat<(i32 (fp_to_sint FPR32:$Rn)), (FCVTZSws FPR32:$Rn)>;
-def : Pat<(i64 (fp_to_sint FPR32:$Rn)), (FCVTZSxs FPR32:$Rn)>;
-def : Pat<(i32 (fp_to_uint FPR32:$Rn)), (FCVTZUws FPR32:$Rn)>;
-def : Pat<(i64 (fp_to_uint FPR32:$Rn)), (FCVTZUxs FPR32:$Rn)>;
-def : Pat<(i32 (fp_to_sint (f64 FPR64:$Rn))), (FCVTZSwd FPR64:$Rn)>;
-def : Pat<(i64 (fp_to_sint (f64 FPR64:$Rn))), (FCVTZSxd FPR64:$Rn)>;
-def : Pat<(i32 (fp_to_uint (f64 FPR64:$Rn))), (FCVTZUwd FPR64:$Rn)>;
-def : Pat<(i64 (fp_to_uint (f64 FPR64:$Rn))), (FCVTZUxd FPR64:$Rn)>;
-
-multiclass A64I_inttofp<bit o0, string asmop>
-{
+let Predicates = [HasFPARMv8] in {
+def : Pat<(i32 (fp_to_sint f32:$Rn)), (FCVTZSws $Rn)>;
+def : Pat<(i64 (fp_to_sint f32:$Rn)), (FCVTZSxs $Rn)>;
+def : Pat<(i32 (fp_to_uint f32:$Rn)), (FCVTZUws $Rn)>;
+def : Pat<(i64 (fp_to_uint f32:$Rn)), (FCVTZUxs $Rn)>;
+def : Pat<(i32 (fp_to_sint f64:$Rn)), (FCVTZSwd $Rn)>;
+def : Pat<(i64 (fp_to_sint f64:$Rn)), (FCVTZSxd $Rn)>;
+def : Pat<(i32 (fp_to_uint f64:$Rn)), (FCVTZUwd $Rn)>;
+def : Pat<(i64 (fp_to_uint f64:$Rn)), (FCVTZUxd $Rn)>;
+}
+
+multiclass A64I_inttofp<bit o0, string asmop> {
def CVTFsw : A64I_fpintI<0b0, 0b00, 0b00, {0, 1, o0}, FPR32, GPR32, asmop>;
def CVTFsx : A64I_fpintI<0b1, 0b00, 0b00, {0, 1, o0}, FPR32, GPR64, asmop>;
def CVTFdw : A64I_fpintI<0b0, 0b01, 0b00, {0, 1, o0}, FPR64, GPR32, asmop>;
defm S : A64I_inttofp<0b0, "scvtf">;
defm U : A64I_inttofp<0b1, "ucvtf">;
-def : Pat<(f32 (sint_to_fp GPR32:$Rn)), (SCVTFsw GPR32:$Rn)>;
-def : Pat<(f32 (sint_to_fp GPR64:$Rn)), (SCVTFsx GPR64:$Rn)>;
-def : Pat<(f64 (sint_to_fp GPR32:$Rn)), (SCVTFdw GPR32:$Rn)>;
-def : Pat<(f64 (sint_to_fp GPR64:$Rn)), (SCVTFdx GPR64:$Rn)>;
-def : Pat<(f32 (uint_to_fp GPR32:$Rn)), (UCVTFsw GPR32:$Rn)>;
-def : Pat<(f32 (uint_to_fp GPR64:$Rn)), (UCVTFsx GPR64:$Rn)>;
-def : Pat<(f64 (uint_to_fp GPR32:$Rn)), (UCVTFdw GPR32:$Rn)>;
-def : Pat<(f64 (uint_to_fp GPR64:$Rn)), (UCVTFdx GPR64:$Rn)>;
+let Predicates = [HasFPARMv8] in {
+def : Pat<(f32 (sint_to_fp i32:$Rn)), (SCVTFsw $Rn)>;
+def : Pat<(f32 (sint_to_fp i64:$Rn)), (SCVTFsx $Rn)>;
+def : Pat<(f64 (sint_to_fp i32:$Rn)), (SCVTFdw $Rn)>;
+def : Pat<(f64 (sint_to_fp i64:$Rn)), (SCVTFdx $Rn)>;
+def : Pat<(f32 (uint_to_fp i32:$Rn)), (UCVTFsw $Rn)>;
+def : Pat<(f32 (uint_to_fp i64:$Rn)), (UCVTFsx $Rn)>;
+def : Pat<(f64 (uint_to_fp i32:$Rn)), (UCVTFdw $Rn)>;
+def : Pat<(f64 (uint_to_fp i64:$Rn)), (UCVTFdx $Rn)>;
+}
def FMOVws : A64I_fpintI<0b0, 0b00, 0b00, 0b110, GPR32, FPR32, "fmov">;
def FMOVsw : A64I_fpintI<0b0, 0b00, 0b00, 0b111, FPR32, GPR32, "fmov">;
def FMOVxd : A64I_fpintI<0b1, 0b01, 0b00, 0b110, GPR64, FPR64, "fmov">;
def FMOVdx : A64I_fpintI<0b1, 0b01, 0b00, 0b111, FPR64, GPR64, "fmov">;
-def : Pat<(i32 (bitconvert (f32 FPR32:$Rn))), (FMOVws FPR32:$Rn)>;
-def : Pat<(f32 (bitconvert (i32 GPR32:$Rn))), (FMOVsw GPR32:$Rn)>;
-def : Pat<(i64 (bitconvert (f64 FPR64:$Rn))), (FMOVxd FPR64:$Rn)>;
-def : Pat<(f64 (bitconvert (i64 GPR64:$Rn))), (FMOVdx GPR64:$Rn)>;
+let Predicates = [HasFPARMv8] in {
+def : Pat<(i32 (bitconvert f32:$Rn)), (FMOVws $Rn)>;
+def : Pat<(f32 (bitconvert i32:$Rn)), (FMOVsw $Rn)>;
+def : Pat<(i64 (bitconvert f64:$Rn)), (FMOVxd $Rn)>;
+def : Pat<(f64 (bitconvert i64:$Rn)), (FMOVdx $Rn)>;
+}
-def lane1_asmoperand : AsmOperandClass
-{
+def lane1_asmoperand : AsmOperandClass {
let Name = "Lane1";
let RenderMethod = "addImmOperands";
+ let DiagnosticType = "Lane1";
}
-def lane1 : Operand<i32>
-{
+def lane1 : Operand<i32> {
let ParserMatchClass = lane1_asmoperand;
let PrintMethod = "printBareImmOperand";
}
-let DecoderMethod = "DecodeFMOVLaneInstruction" in
-{
+let DecoderMethod = "DecodeFMOVLaneInstruction" in {
def FMOVxv : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b110,
(outs GPR64:$Rd), (ins VPR128:$Rn, lane1:$Lane),
"fmov\t$Rd, $Rn.d[$Lane]", [], NoItinerary>;
"fmov\t$Rd.d[$Lane], $Rn", [], NoItinerary>;
}
+let Predicates = [HasFPARMv8] in {
def : InstAlias<"fmov $Rd, $Rn.2d[$Lane]",
(FMOVxv GPR64:$Rd, VPR128:$Rn, lane1:$Lane), 0b0>;
def : InstAlias<"fmov $Rd.2d[$Lane], $Rn",
(FMOVvx VPR128:$Rd, GPR64:$Rn, lane1:$Lane), 0b0>;
+}
//===----------------------------------------------------------------------===//
// Floating-point immediate instructions
//===----------------------------------------------------------------------===//
// Contains: FMOV
-def fpimm_asmoperand : AsmOperandClass
-{
+def fpimm_asmoperand : AsmOperandClass {
let Name = "FMOVImm";
let ParserMethod = "ParseFPImmOperand";
+ let DiagnosticType = "FPImm";
}
// The MCOperand for these instructions are the encoded 8-bit values.
class fmov_operand<ValueType FT>
: Operand<i32>,
PatLeaf<(FT fpimm), [{ return A64Imms::isFPImm(N->getValueAPF()); }],
- SDXF_fpimm>
-{
+ SDXF_fpimm> {
let PrintMethod = "printFPImmOperand";
let ParserMatchClass = fpimm_asmoperand;
}
(outs Reg:$Rd),
(ins fmov_operand:$Imm8),
"fmov\t$Rd, $Imm8",
- [(set (VT Reg:$Rd), fmov_operand:$Imm8)],
+ [(set VT:$Rd, fmov_operand:$Imm8)],
NoItinerary>;
def FMOVsi : A64I_fpimm_impl<0b00, FPR32, f32, fmov32_operand>;
//===----------------------------------------------------------------------===//
// Contains: LDR, LDRSW, PRFM
-def ldrlit_label_asmoperand : AsmOperandClass
-{
+def ldrlit_label_asmoperand : AsmOperandClass {
let Name = "LoadLitLabel";
let RenderMethod = "addLabelOperands<19, 4>";
+ let DiagnosticType = "Label";
}
-def ldrlit_label : Operand<i64>
-{
+def ldrlit_label : Operand<i64> {
let EncoderMethod = "getLoadLitLabelOpValue";
// This label is a 19-bit offset from PC, scaled by the instruction-width: 4.
// Various instructions take an immediate value (which can always be used),
// where some numbers have a symbolic name to make things easier. These operands
// and the associated functions abstract away the differences.
-multiclass namedimm<string prefix, string mapper>
-{
- def _asmoperand : AsmOperandClass
- {
+multiclass namedimm<string prefix, string mapper> {
+ def _asmoperand : AsmOperandClass {
let Name = "NamedImm" # prefix;
let PredicateMethod = "isUImm";
let RenderMethod = "addImmOperands";
let ParserMethod = "ParseNamedImmOperand<" # mapper # ">";
+ let DiagnosticType = "NamedImm_" # prefix;
}
- def _op : Operand<i32>
- {
+ def _op : Operand<i32> {
let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
let PrintMethod = "printNamedImmOperand<" # mapper # ">";
let DecoderMethod = "DecodeNamedImmOperand<" # mapper # ">";
: A64I_LDRlit<opc, v, (outs OutReg:$Rt), (ins ldrlit_label:$Imm19),
"ldr\t$Rt, $Imm19", patterns, NoItinerary>;
-let mayLoad = 1 in
-{
+let mayLoad = 1 in {
def LDRw_lit : A64I_LDRlitSimple<0b00, 0b0, GPR32>;
def LDRx_lit : A64I_LDRlitSimple<0b01, 0b0, GPR64>;
}
-def LDRs_lit : A64I_LDRlitSimple<0b00, 0b1, FPR32,
- [(set (f32 FPR32:$Rt), (load constpool:$Imm19))]>;
-def LDRd_lit : A64I_LDRlitSimple<0b01, 0b1, FPR64,
- [(set (f64 FPR64:$Rt), (load constpool:$Imm19))]>;
+let Predicates = [HasFPARMv8] in {
+def LDRs_lit : A64I_LDRlitSimple<0b00, 0b1, FPR32>;
+def LDRd_lit : A64I_LDRlitSimple<0b01, 0b1, FPR64>;
+}
-let mayLoad = 1 in
-{
+let mayLoad = 1 in {
+ let Predicates = [HasFPARMv8] in {
def LDRq_lit : A64I_LDRlitSimple<0b10, 0b1, FPR128>;
+ }
def LDRSWx_lit : A64I_LDRlit<0b10, 0b0,
// This operand parses a GPR64xsp register, followed by an optional immediate
// #0.
-def GPR64xsp0_asmoperand : AsmOperandClass
-{
+def GPR64xsp0_asmoperand : AsmOperandClass {
let Name = "GPR64xsp0";
let PredicateMethod = "isWrappedReg";
let RenderMethod = "addRegOperands";
let ParserMethod = "ParseLSXAddressOperand";
+ // Diagnostics are provided by ParserMethod
}
-def GPR64xsp0 : RegisterOperand<GPR64xsp>
-{
+def GPR64xsp0 : RegisterOperand<GPR64xsp> {
let ParserMatchClass = GPR64xsp0_asmoperand;
}
class A64I_SRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
dag ins, list<dag> pat,
InstrItinClass itin> :
- A64I_LDSTex_stn <size,
+ A64I_LDSTex_stn <size,
opcode{2}, 0, opcode{1}, opcode{0},
outs, ins,
!strconcat(asm, "\t$Rs, $Rt, [$Rn]"),
class A64I_LRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
dag ins, list<dag> pat,
InstrItinClass itin> :
- A64I_LDSTex_tn <size,
+ A64I_LDSTex_tn <size,
opcode{2}, 1, opcode{1}, opcode{0},
outs, ins,
!strconcat(asm, "\t$Rt, [$Rn]"),
class acquiring_load<PatFrag base>
: PatFrag<(ops node:$ptr), (base node:$ptr), [{
- return cast<AtomicSDNode>(N)->getOrdering() == Acquire;
+ AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
+ return Ordering == Acquire || Ordering == SequentiallyConsistent;
}]>;
def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
def atomic_load_acquire_64 : acquiring_load<atomic_load_64>;
-def : Pat<(atomic_load_acquire_8 GPR64xsp:$Rn), (LDAR_byte GPR64xsp0:$Rn)>;
-def : Pat<(atomic_load_acquire_16 GPR64xsp:$Rn), (LDAR_hword GPR64xsp0:$Rn)>;
-def : Pat<(atomic_load_acquire_32 GPR64xsp:$Rn), (LDAR_word GPR64xsp0:$Rn)>;
-def : Pat<(atomic_load_acquire_64 GPR64xsp:$Rn), (LDAR_dword GPR64xsp0:$Rn)>;
+def : Pat<(atomic_load_acquire_8 i64:$Rn), (LDAR_byte $Rn)>;
+def : Pat<(atomic_load_acquire_16 i64:$Rn), (LDAR_hword $Rn)>;
+def : Pat<(atomic_load_acquire_32 i64:$Rn), (LDAR_word $Rn)>;
+def : Pat<(atomic_load_acquire_64 i64:$Rn), (LDAR_dword $Rn)>;
//===----------------------------------
// Store-release (no exclusivity)
class A64I_SLexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
dag ins, list<dag> pat,
InstrItinClass itin> :
- A64I_LDSTex_tn <size,
+ A64I_LDSTex_tn <size,
opcode{2}, 0, opcode{1}, opcode{0},
outs, ins,
!strconcat(asm, "\t$Rt, [$Rn]"),
class releasing_store<PatFrag base>
: PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
- return cast<AtomicSDNode>(N)->getOrdering() == Release;
+ AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
+ return Ordering == Release || Ordering == SequentiallyConsistent;
}]>;
def atomic_store_release_8 : releasing_store<atomic_store_8>;
multiclass A64I_SLex<string asmstr, bits<3> opcode, string prefix> {
def _byte: A64I_SLexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
(outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
- [(atomic_store_release_8 GPR64xsp0:$Rn, GPR32:$Rt)],
+ [(atomic_store_release_8 i64:$Rn, i32:$Rt)],
NoItinerary>;
def _hword: A64I_SLexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
(outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
- [(atomic_store_release_16 GPR64xsp0:$Rn, GPR32:$Rt)],
+ [(atomic_store_release_16 i64:$Rn, i32:$Rt)],
NoItinerary>;
def _word: A64I_SLexs_impl<0b10, opcode, asmstr,
(outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
- [(atomic_store_release_32 GPR64xsp0:$Rn, GPR32:$Rt)],
+ [(atomic_store_release_32 i64:$Rn, i32:$Rt)],
NoItinerary>;
def _dword: A64I_SLexs_impl<0b11, opcode, asmstr,
(outs), (ins GPR64:$Rt, GPR64xsp0:$Rn),
- [(atomic_store_release_64 GPR64xsp0:$Rn, GPR64:$Rt)],
+ [(atomic_store_release_64 i64:$Rn, i64:$Rt)],
NoItinerary>;
}
class A64I_SPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
dag ins, list<dag> pat,
InstrItinClass itin> :
- A64I_LDSTex_stt2n <size,
+ A64I_LDSTex_stt2n <size,
opcode{2}, 0, opcode{1}, opcode{0},
outs, ins,
!strconcat(asm, "\t$Rs, $Rt, $Rt2, [$Rn]"),
- pat, itin>
-{
+ pat, itin> {
let mayStore = 1;
}
class A64I_LPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
dag ins, list<dag> pat,
InstrItinClass itin> :
- A64I_LDSTex_tt2n <size,
+ A64I_LDSTex_tt2n <size,
opcode{2}, 1, opcode{1}, opcode{0},
outs, ins,
!strconcat(asm, "\t$Rt, $Rt2, [$Rn]"),
// 1.1 Unsigned 12-bit immediate operands
//===-------------------------------
-multiclass offsets_uimm12<int MemSize, string prefix>
-{
- def uimm12_asmoperand : AsmOperandClass
- {
+multiclass offsets_uimm12<int MemSize, string prefix> {
+ def uimm12_asmoperand : AsmOperandClass {
let Name = "OffsetUImm12_" # MemSize;
let PredicateMethod = "isOffsetUImm12<" # MemSize # ">";
let RenderMethod = "addOffsetUImm12Operands<" # MemSize # ">";
+ let DiagnosticType = "LoadStoreUImm12_" # MemSize;
}
// Pattern is really no more than an ImmLeaf, but predicated on MemSize which
// complicates things beyond TableGen's ken.
def uimm12 : Operand<i64>,
- ComplexPattern<i64, 1, "SelectOffsetUImm12<" # MemSize # ">">
- {
+ ComplexPattern<i64, 1, "SelectOffsetUImm12<" # MemSize # ">"> {
let ParserMatchClass
= !cast<AsmOperandClass>(prefix # uimm12_asmoperand);
return CurDAG->getTargetConstant(N->getZExtValue() & 0x1ff, MVT::i32);
}]>;
-def simm9_asmoperand : AsmOperandClass
-{
+def simm9_asmoperand : AsmOperandClass {
let Name = "SImm9";
let PredicateMethod = "isSImm<9>";
let RenderMethod = "addSImmOperands<9>";
+ let DiagnosticType = "LoadStoreSImm9";
}
def simm9 : Operand<i64>,
ImmLeaf<i64, [{ return Imm >= -0x100 && Imm <= 0xff; }],
- SDXF_simm9>
-{
+ SDXF_simm9> {
let PrintMethod = "printOffsetSImm9Operand";
let ParserMatchClass = simm9_asmoperand;
}
// which will need separate instructions for LLVM type-consistency. We'll also
// need separate operands, of course.
multiclass regexts<int MemSize, int RmSize, RegisterClass GPR,
- string Rm, string prefix>
-{
- def regext_asmoperand : AsmOperandClass
- {
+ string Rm, string prefix> {
+ def regext_asmoperand : AsmOperandClass {
let Name = "AddrRegExtend_" # MemSize # "_" # Rm;
let PredicateMethod = "isAddrRegExtend<" # MemSize # "," # RmSize # ">";
let RenderMethod = "addAddrRegExtendOperands<" # MemSize # ">";
+ let DiagnosticType = "LoadStoreExtend" # RmSize # "_" # MemSize;
}
- def regext : Operand<i64>
- {
+ def regext : Operand<i64> {
let PrintMethod
= "printAddrRegExtendOperand<" # MemSize # ", " # RmSize # ">";
}
}
-multiclass regexts_wx<int MemSize, string prefix>
-{
+multiclass regexts_wx<int MemSize, string prefix> {
// Rm is an X-register if LSL or SXTX are specified as the shift.
defm Xm_ : regexts<MemSize, 64, GPR64, "Xm", prefix # "Xm_">;
// This class covers the basic unsigned or irrelevantly-signed loads and stores,
// to general-purpose and floating-point registers.
-class AddrParams<string prefix>
-{
+class AddrParams<string prefix> {
Operand uimm12 = !cast<Operand>(prefix # "_uimm12");
Operand regextWm = !cast<Operand>(prefix # "_Wm_regext");
multiclass A64I_LDRSTR_unsigned<string prefix, bits<2> size, bit v,
bit high_opc, string asmsuffix,
- RegisterClass GPR, AddrParams params>
-{
+ RegisterClass GPR, AddrParams params> {
// Unsigned immediate
def _STR : A64I_LSunsigimm<size, v, {high_opc, 0b0},
(outs), (ins GPR:$Rt, GPR64xsp:$Rn, params.uimm12:$UImm12),
"str" # asmsuffix # "\t$Rt, [$Rn, $UImm12]",
- [], NoItinerary>
- {
+ [], NoItinerary> {
let mayStore = 1;
}
def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn]",
def _LDR : A64I_LSunsigimm<size, v, {high_opc, 0b1},
(outs GPR:$Rt), (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
"ldr" # asmsuffix # "\t$Rt, [$Rn, $UImm12]",
- [], NoItinerary>
- {
+ [], NoItinerary> {
let mayLoad = 1;
}
def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn]",
(!cast<Instruction>(prefix # "_LDR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
// Register offset (four of these: load/store and Wm/Xm).
- let mayLoad = 1 in
- {
+ let mayLoad = 1 in {
def _Wm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b0,
(outs GPR:$Rt),
(ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
(!cast<Instruction>(prefix # "_Xm_RegOffset_LDR") GPR:$Rt, GPR64xsp:$Rn,
GPR64:$Rm, 2)>;
- let mayStore = 1 in
- {
+ let mayStore = 1 in {
def _Wm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b0,
(outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR32:$Rm,
params.regextWm:$Ext),
def _STUR : A64I_LSunalimm<size, v, {high_opc, 0b0},
(outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
"stur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
- [], NoItinerary>
- {
+ [], NoItinerary> {
let mayStore = 1;
}
def : InstAlias<"stur" # asmsuffix # " $Rt, [$Rn]",
def _LDUR : A64I_LSunalimm<size, v, {high_opc, 0b1},
(outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),
"ldur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
- [], NoItinerary>
- {
+ [], NoItinerary> {
let mayLoad = 1;
}
def : InstAlias<"ldur" # asmsuffix # " $Rt, [$Rn]",
(outs GPR64xsp:$Rn_wb),
(ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
"str" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
- [], NoItinerary>
- {
+ [], NoItinerary> {
let Constraints = "$Rn = $Rn_wb";
let mayStore = 1;
(outs GPR:$Rt, GPR64xsp:$Rn_wb),
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldr" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
- [], NoItinerary>
- {
+ [], NoItinerary> {
let mayLoad = 1;
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeSingleIndexedInstruction";
(outs GPR64xsp:$Rn_wb),
(ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
"str" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
- [], NoItinerary>
- {
+ [], NoItinerary> {
let Constraints = "$Rn = $Rn_wb";
let mayStore = 1;
(outs GPR:$Rt, GPR64xsp:$Rn_wb),
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
- [], NoItinerary>
- {
+ [], NoItinerary> {
let mayLoad = 1;
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeSingleIndexedInstruction";
defm LS64
: A64I_LDRSTR_unsigned<"LS64", 0b11, 0b0, 0b0, "", GPR64, dword_addrparams>;
+let Predicates = [HasFPARMv8] in {
// STR/LDR to/from a B register
defm LSFP8
: A64I_LDRSTR_unsigned<"LSFP8", 0b00, 0b1, 0b0, "", FPR8, byte_addrparams>;
: A64I_LDRSTR_unsigned<"LSFP64", 0b11, 0b1, 0b0, "", FPR64, dword_addrparams>;
// STR/LDR to/from a Q register
defm LSFP128
- : A64I_LDRSTR_unsigned<"LSFP128", 0b00, 0b1, 0b1, "", FPR128, qword_addrparams>;
+ : A64I_LDRSTR_unsigned<"LSFP128", 0b00, 0b1, 0b1, "", FPR128,
+ qword_addrparams>;
+}
//===------------------------------
// 2.3 Signed loads
// so it's worth factoring out. Signed word loads don't fit because there is no
// W version.
multiclass A64I_LDR_signed<bits<2> size, string asmopcode, AddrParams params,
- string prefix>
-{
+ string prefix> {
// Unsigned offset
def w : A64I_LSunsigimm<size, 0b0, 0b11,
(outs GPR32:$Rt),
(ins GPR64xsp:$Rn, params.uimm12:$UImm12),
"ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",
- [], NoItinerary>
- {
+ [], NoItinerary> {
let mayLoad = 1;
}
def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",
(outs GPR64:$Rt),
(ins GPR64xsp:$Rn, params.uimm12:$UImm12),
"ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",
- [], NoItinerary>
- {
+ [], NoItinerary> {
let mayLoad = 1;
}
def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",
(!cast<Instruction>(prefix # x) GPR64:$Rt, GPR64xsp:$Rn, 0)>;
// Register offset
- let mayLoad = 1 in
- {
+ let mayLoad = 1 in {
def w_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b0,
(outs GPR32:$Rt),
(ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
GPR64:$Rm, 2)>;
- let mayLoad = 1 in
- {
+ let mayLoad = 1 in {
// Unaligned offset
def w_U : A64I_LSunalimm<size, 0b0, 0b11,
(outs GPR32:$Rt),
(outs GPR32:$Rt, GPR64xsp:$Rn_wb),
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
- [], NoItinerary>
- {
+ [], NoItinerary> {
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeSingleIndexedInstruction";
}
(outs GPR64:$Rt, GPR64xsp:$Rn_wb),
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
- [], NoItinerary>
- {
+ [], NoItinerary> {
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeSingleIndexedInstruction";
}
(outs GPR32:$Rt, GPR64xsp:$Rn_wb),
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
- [], NoItinerary>
- {
+ [], NoItinerary> {
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeSingleIndexedInstruction";
}
(outs GPR64:$Rt, GPR64xsp:$Rn_wb),
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
- [], NoItinerary>
- {
+ [], NoItinerary> {
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeSingleIndexedInstruction";
}
(outs GPR64:$Rt),
(ins GPR64xsp:$Rn, word_uimm12:$UImm12),
"ldrsw\t$Rt, [$Rn, $UImm12]",
- [], NoItinerary>
-{
+ [], NoItinerary> {
let mayLoad = 1;
}
def : InstAlias<"ldrsw $Rt, [$Rn]", (LDRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
-let mayLoad = 1 in
-{
+let mayLoad = 1 in {
def LDRSWx_Wm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b0,
(outs GPR64:$Rt),
(ins GPR64xsp:$Rn, GPR32:$Rm, word_Wm_regext:$Ext),
(outs GPR64:$Rt),
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldursw\t$Rt, [$Rn, $SImm9]",
- [], NoItinerary>
-{
+ [], NoItinerary> {
let mayLoad = 1;
}
def : InstAlias<"ldursw $Rt, [$Rn]", (LDURSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
(outs GPR64:$Rt, GPR64xsp:$Rn_wb),
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldrsw\t$Rt, [$Rn], $SImm9",
- [], NoItinerary>
-{
+ [], NoItinerary> {
let mayLoad = 1;
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeSingleIndexedInstruction";
(outs GPR64:$Rt, GPR64xsp:$Rn_wb),
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldrsw\t$Rt, [$Rn, $SImm9]!",
- [], NoItinerary>
-{
+ [], NoItinerary> {
let mayLoad = 1;
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeSingleIndexedInstruction";
def PRFM : A64I_LSunsigimm<0b11, 0b0, 0b10, (outs),
(ins prefetch_op:$Rt, GPR64xsp:$Rn, dword_uimm12:$UImm12),
"prfm\t$Rt, [$Rn, $UImm12]",
- [], NoItinerary>
-{
+ [], NoItinerary> {
let mayLoad = 1;
}
def : InstAlias<"prfm $Rt, [$Rn]",
(PRFM prefetch_op:$Rt, GPR64xsp:$Rn, 0)>;
-let mayLoad = 1 in
-{
+let mayLoad = 1 in {
def PRFM_Wm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b0, (outs),
(ins prefetch_op:$Rt, GPR64xsp:$Rn,
GPR32:$Rm, dword_Wm_regext:$Ext),
def PRFUM : A64I_LSunalimm<0b11, 0b0, 0b10, (outs),
(ins prefetch_op:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
"prfum\t$Rt, [$Rn, $SImm9]",
- [], NoItinerary>
-{
+ [], NoItinerary> {
let mayLoad = 1;
}
def : InstAlias<"prfum $Rt, [$Rn]",
// section to avoid instantiation of "ldtr d0, [sp]" etc.
multiclass A64I_LDTRSTTR<bits<2> size, string asmsuffix, RegisterClass GPR,
- string prefix>
-{
+ string prefix> {
def _UnPriv_STR : A64I_LSunpriv<size, 0b0, 0b00,
(outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
"sttr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
- [], NoItinerary>
- {
+ [], NoItinerary> {
let mayStore = 1;
}
def _UnPriv_LDR : A64I_LSunpriv<size, 0b0, 0b01,
(outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),
"ldtr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
- [], NoItinerary>
- {
+ [], NoItinerary> {
let mayLoad = 1;
}
// Now a class for the signed instructions that can go to either 32 or 64
// bits...
-multiclass A64I_LDTR_signed<bits<2> size, string asmopcode, string prefix>
-{
- let mayLoad = 1 in
- {
+multiclass A64I_LDTR_signed<bits<2> size, string asmopcode, string prefix> {
+ let mayLoad = 1 in {
def w : A64I_LSunpriv<size, 0b0, 0b11,
(outs GPR32:$Rt),
(ins GPR64xsp:$Rn, simm9:$SImm9),
(outs GPR64:$Rt),
(ins GPR64xsp:$Rn, simm9:$SImm9),
"ldtrsw\t$Rt, [$Rn, $SImm9]",
- [], NoItinerary>
-{
+ [], NoItinerary> {
let mayLoad = 1;
}
def : InstAlias<"ldtrsw $Rt, [$Rn]", (LDTRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
// Operands for each access size. This multiclass takes care of instantiating
// the correct template functions in the rest of the backend.
-multiclass offsets_simm7<string MemSize, string prefix>
-{
+multiclass offsets_simm7<string MemSize, string prefix> {
// The bare signed 7-bit immediate is used in post-indexed instructions, but
// because of the scaling performed a generic "simm7" operand isn't
// appropriate here either.
- def simm7_asmoperand : AsmOperandClass
- {
+ def simm7_asmoperand : AsmOperandClass {
let Name = "SImm7_Scaled" # MemSize;
let PredicateMethod = "isSImm7Scaled<" # MemSize # ">";
let RenderMethod = "addSImm7ScaledOperands<" # MemSize # ">";
+ let DiagnosticType = "LoadStoreSImm7_" # MemSize;
}
- def simm7 : Operand<i64>
- {
+ def simm7 : Operand<i64> {
let PrintMethod = "printSImm7ScaledOperand<" # MemSize # ">";
let ParserMatchClass = !cast<AsmOperandClass>(prefix # "simm7_asmoperand");
}
defm qword_ : offsets_simm7<"16", "qword_">;
multiclass A64I_LSPsimple<bits<2> opc, bit v, RegisterClass SomeReg,
- Operand simm7, string prefix>
-{
+ Operand simm7, string prefix> {
def _STR : A64I_LSPoffset<opc, v, 0b0, (outs),
(ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
- "stp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>
- {
+ "stp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
let mayStore = 1;
let DecoderMethod = "DecodeLDSTPairInstruction";
}
def _LDR : A64I_LSPoffset<opc, v, 0b1,
(outs SomeReg:$Rt, SomeReg:$Rt2),
(ins GPR64xsp:$Rn, simm7:$SImm7),
- "ldp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>
- {
+ "ldp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
let mayLoad = 1;
let DecoderMethod = "DecodeLDSTPairInstruction";
}
GPR64xsp:$Rn,
simm7:$SImm7),
"stp\t$Rt, $Rt2, [$Rn], $SImm7",
- [], NoItinerary>
- {
+ [], NoItinerary> {
let mayStore = 1;
let Constraints = "$Rn = $Rn_wb";
(outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),
(ins GPR64xsp:$Rn, simm7:$SImm7),
"ldp\t$Rt, $Rt2, [$Rn], $SImm7",
- [], NoItinerary>
- {
+ [], NoItinerary> {
let mayLoad = 1;
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeLDSTPairInstruction";
def _PreInd_STR : A64I_LSPpreind<opc, v, 0b0, (outs GPR64xsp:$Rn_wb),
(ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
"stp\t$Rt, $Rt2, [$Rn, $SImm7]!",
- [], NoItinerary>
- {
+ [], NoItinerary> {
let mayStore = 1;
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeLDSTPairInstruction";
(outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),
(ins GPR64xsp:$Rn, simm7:$SImm7),
"ldp\t$Rt, $Rt2, [$Rn, $SImm7]!",
- [], NoItinerary>
- {
+ [], NoItinerary> {
let mayLoad = 1;
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeLDSTPairInstruction";
def _NonTemp_STR : A64I_LSPnontemp<opc, v, 0b0, (outs),
(ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
- "stnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>
- {
+ "stnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
let mayStore = 1;
let DecoderMethod = "DecodeLDSTPairInstruction";
}
def _NonTemp_LDR : A64I_LSPnontemp<opc, v, 0b1,
(outs SomeReg:$Rt, SomeReg:$Rt2),
(ins GPR64xsp:$Rn, simm7:$SImm7),
- "ldnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>
- {
+ "ldnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
let mayLoad = 1;
let DecoderMethod = "DecodeLDSTPairInstruction";
}
defm LSPair32 : A64I_LSPsimple<0b00, 0b0, GPR32, word_simm7, "LSPair32">;
defm LSPair64 : A64I_LSPsimple<0b10, 0b0, GPR64, dword_simm7, "LSPair64">;
+
+let Predicates = [HasFPARMv8] in {
defm LSFPPair32 : A64I_LSPsimple<0b00, 0b1, FPR32, word_simm7, "LSFPPair32">;
defm LSFPPair64 : A64I_LSPsimple<0b01, 0b1, FPR64, dword_simm7, "LSFPPair64">;
-defm LSFPPair128 : A64I_LSPsimple<0b10, 0b1, FPR128, qword_simm7, "LSFPPair128">;
+defm LSFPPair128 : A64I_LSPsimple<0b10, 0b1, FPR128, qword_simm7,
+ "LSFPPair128">;
+}
def LDPSWx : A64I_LSPoffset<0b01, 0b0, 0b1,
(outs GPR64:$Rt, GPR64:$Rt2),
(ins GPR64xsp:$Rn, word_simm7:$SImm7),
- "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>
-{
+ "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
let mayLoad = 1;
let DecoderMethod = "DecodeLDSTPairInstruction";
}
(outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb),
(ins GPR64xsp:$Rn, word_simm7:$SImm7),
"ldpsw\t$Rt, $Rt2, [$Rn], $SImm7",
- [], NoItinerary>
-{
+ [], NoItinerary> {
let mayLoad = 1;
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeLDSTPairInstruction";
(outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb),
(ins GPR64xsp:$Rn, word_simm7:$SImm7),
"ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]!",
- [], NoItinerary>
-{
+ [], NoItinerary> {
let mayLoad = 1;
let Constraints = "$Rn = $Rn_wb";
let DecoderMethod = "DecodeLDSTPairInstruction";
// Contains: AND, ORR, EOR, ANDS, + aliases TST, MOV
multiclass logical_imm_operands<string prefix, string note,
- int size, ValueType VT>
-{
- def _asmoperand : AsmOperandClass
- {
+ int size, ValueType VT> {
+ def _asmoperand : AsmOperandClass {
let Name = "LogicalImm" # note # size;
let PredicateMethod = "isLogicalImm" # note # "<" # size # ">";
let RenderMethod = "addLogicalImmOperands<" # size # ">";
+ let DiagnosticType = "LogicalSecondSource";
}
def _operand
- : Operand<VT>, ComplexPattern<VT, 1, "SelectLogicalImm", [imm]>
- {
+ : Operand<VT>, ComplexPattern<VT, 1, "SelectLogicalImm", [imm]> {
let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
let PrintMethod = "printLogicalImmOperand<" # size # ">";
let DecoderMethod = "DecodeLogicalImmOperand<" # size # ">";
: logical_imm_operands<"logical_imm64_mov", "MOV", 64, i64>;
-multiclass A64I_logimmSizes<bits<2> opc, string asmop, SDNode opnode>
-{
+multiclass A64I_logimmSizes<bits<2> opc, string asmop, SDNode opnode> {
def wwi : A64I_logicalimm<0b0, opc, (outs GPR32wsp:$Rd),
(ins GPR32:$Rn, logical_imm32_operand:$Imm),
!strconcat(asmop, "\t$Rd, $Rn, $Imm"),
- [(set GPR32wsp:$Rd,
- (opnode GPR32:$Rn, logical_imm32_operand:$Imm))],
+ [(set i32:$Rd,
+ (opnode i32:$Rn, logical_imm32_operand:$Imm))],
NoItinerary>;
def xxi : A64I_logicalimm<0b1, opc, (outs GPR64xsp:$Rd),
(ins GPR64:$Rn, logical_imm64_operand:$Imm),
!strconcat(asmop, "\t$Rd, $Rn, $Imm"),
- [(set GPR64xsp:$Rd,
- (opnode GPR64:$Rn, logical_imm64_operand:$Imm))],
+ [(set i64:$Rd,
+ (opnode i64:$Rn, logical_imm64_operand:$Imm))],
NoItinerary>;
}
defm ORR : A64I_logimmSizes<0b01, "orr", or>;
defm EOR : A64I_logimmSizes<0b10, "eor", xor>;
-let Defs = [NZCV] in
-{
+let Defs = [NZCV] in {
def ANDSwwi : A64I_logicalimm<0b0, 0b11, (outs GPR32:$Rd),
(ins GPR32:$Rn, logical_imm32_operand:$Imm),
"ands\t$Rd, $Rn, $Imm",
// when the revolution comes.
multiclass logical_shifts<string prefix, bit sf, bits<2> opc,
bit N, bit commutable,
- string asmop, SDPatternOperator opfrag, string sty,
- RegisterClass GPR, list<Register> defs>
-{
+ string asmop, SDPatternOperator opfrag, ValueType ty,
+ RegisterClass GPR, list<Register> defs> {
let isCommutable = commutable, Defs = defs in {
def _lsl : A64I_logicalshift<sf, opc, 0b00, N,
(outs GPR:$Rd),
(ins GPR:$Rn, GPR:$Rm,
- !cast<Operand>("lsl_operand_" # sty):$Imm6),
+ !cast<Operand>("lsl_operand_" # ty):$Imm6),
!strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
- [(set GPR:$Rd, (opfrag GPR:$Rn, (shl GPR:$Rm,
- !cast<Operand>("lsl_operand_" # sty):$Imm6))
+ [(set ty:$Rd, (opfrag ty:$Rn, (shl ty:$Rm,
+ !cast<Operand>("lsl_operand_" # ty):$Imm6))
)],
NoItinerary>;
def _lsr : A64I_logicalshift<sf, opc, 0b01, N,
(outs GPR:$Rd),
(ins GPR:$Rn, GPR:$Rm,
- !cast<Operand>("lsr_operand_" # sty):$Imm6),
+ !cast<Operand>("lsr_operand_" # ty):$Imm6),
!strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
- [(set GPR:$Rd, (opfrag GPR:$Rn, (srl GPR:$Rm,
- !cast<Operand>("lsr_operand_" # sty):$Imm6))
+ [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm,
+ !cast<Operand>("lsr_operand_" # ty):$Imm6))
)],
NoItinerary>;
def _asr : A64I_logicalshift<sf, opc, 0b10, N,
(outs GPR:$Rd),
(ins GPR:$Rn, GPR:$Rm,
- !cast<Operand>("asr_operand_" # sty):$Imm6),
+ !cast<Operand>("asr_operand_" # ty):$Imm6),
!strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
- [(set GPR:$Rd, (opfrag GPR:$Rn, (sra GPR:$Rm,
- !cast<Operand>("asr_operand_" # sty):$Imm6))
+ [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm,
+ !cast<Operand>("asr_operand_" # ty):$Imm6))
)],
NoItinerary>;
def _ror : A64I_logicalshift<sf, opc, 0b11, N,
(outs GPR:$Rd),
(ins GPR:$Rn, GPR:$Rm,
- !cast<Operand>("ror_operand_" # sty):$Imm6),
+ !cast<Operand>("ror_operand_" # ty):$Imm6),
!strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
- [(set GPR:$Rd, (opfrag GPR:$Rn, (rotr GPR:$Rm,
- !cast<Operand>("ror_operand_" # sty):$Imm6))
+ [(set ty:$Rd, (opfrag ty:$Rn, (rotr ty:$Rm,
+ !cast<Operand>("ror_operand_" # ty):$Imm6))
)],
NoItinerary>;
}
(!cast<Instruction>(prefix # "_lsl") GPR:$Rd, GPR:$Rn,
GPR:$Rm, 0)>;
- def : Pat<(opfrag GPR:$Rn, GPR:$Rm),
- (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
+ def : Pat<(opfrag ty:$Rn, ty:$Rm),
+ (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
}
multiclass logical_sizes<string prefix, bits<2> opc, bit N, bit commutable,
string asmop, SDPatternOperator opfrag,
- list<Register> defs>
-{
+ list<Register> defs> {
defm xxx : logical_shifts<prefix # "xxx", 0b1, opc, N,
- commutable, asmop, opfrag, "i64", GPR64, defs>;
+ commutable, asmop, opfrag, i64, GPR64, defs>;
defm www : logical_shifts<prefix # "www", 0b0, opc, N,
- commutable, asmop, opfrag, "i32", GPR32, defs>;
+ commutable, asmop, opfrag, i32, GPR32, defs>;
}
[{ (void)N; return false; }]>,
[NZCV]>;
-multiclass tst_shifts<string prefix, bit sf, string sty, RegisterClass GPR>
-{
+multiclass tst_shifts<string prefix, bit sf, ValueType ty, RegisterClass GPR> {
let isCommutable = 1, Rd = 0b11111, Defs = [NZCV] in {
def _lsl : A64I_logicalshift<sf, 0b11, 0b00, 0b0,
(outs),
(ins GPR:$Rn, GPR:$Rm,
- !cast<Operand>("lsl_operand_" # sty):$Imm6),
+ !cast<Operand>("lsl_operand_" # ty):$Imm6),
"tst\t$Rn, $Rm, $Imm6",
- [(set NZCV, (A64setcc (and GPR:$Rn, (shl GPR:$Rm,
- !cast<Operand>("lsl_operand_" # sty):$Imm6)),
+ [(set NZCV, (A64setcc (and ty:$Rn, (shl ty:$Rm,
+ !cast<Operand>("lsl_operand_" # ty):$Imm6)),
0, signed_cond))],
NoItinerary>;
def _lsr : A64I_logicalshift<sf, 0b11, 0b01, 0b0,
(outs),
(ins GPR:$Rn, GPR:$Rm,
- !cast<Operand>("lsr_operand_" # sty):$Imm6),
+ !cast<Operand>("lsr_operand_" # ty):$Imm6),
"tst\t$Rn, $Rm, $Imm6",
- [(set NZCV, (A64setcc (and GPR:$Rn, (srl GPR:$Rm,
- !cast<Operand>("lsr_operand_" # sty):$Imm6)),
+ [(set NZCV, (A64setcc (and ty:$Rn, (srl ty:$Rm,
+ !cast<Operand>("lsr_operand_" # ty):$Imm6)),
0, signed_cond))],
NoItinerary>;
def _asr : A64I_logicalshift<sf, 0b11, 0b10, 0b0,
(outs),
(ins GPR:$Rn, GPR:$Rm,
- !cast<Operand>("asr_operand_" # sty):$Imm6),
+ !cast<Operand>("asr_operand_" # ty):$Imm6),
"tst\t$Rn, $Rm, $Imm6",
- [(set NZCV, (A64setcc (and GPR:$Rn, (sra GPR:$Rm,
- !cast<Operand>("asr_operand_" # sty):$Imm6)),
+ [(set NZCV, (A64setcc (and ty:$Rn, (sra ty:$Rm,
+ !cast<Operand>("asr_operand_" # ty):$Imm6)),
0, signed_cond))],
NoItinerary>;
def _ror : A64I_logicalshift<sf, 0b11, 0b11, 0b0,
(outs),
(ins GPR:$Rn, GPR:$Rm,
- !cast<Operand>("ror_operand_" # sty):$Imm6),
+ !cast<Operand>("ror_operand_" # ty):$Imm6),
"tst\t$Rn, $Rm, $Imm6",
- [(set NZCV, (A64setcc (and GPR:$Rn, (rotr GPR:$Rm,
- !cast<Operand>("ror_operand_" # sty):$Imm6)),
+ [(set NZCV, (A64setcc (and ty:$Rn, (rotr ty:$Rm,
+ !cast<Operand>("ror_operand_" # ty):$Imm6)),
0, signed_cond))],
NoItinerary>;
}
def _noshift : InstAlias<"tst $Rn, $Rm",
(!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
- def : Pat<(A64setcc (and GPR:$Rn, GPR:$Rm), 0, signed_cond),
- (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
+ def : Pat<(A64setcc (and ty:$Rn, ty:$Rm), 0, signed_cond),
+ (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
}
-defm TSTxx : tst_shifts<"TSTxx", 0b1, "i64", GPR64>;
-defm TSTww : tst_shifts<"TSTww", 0b0, "i32", GPR32>;
+defm TSTxx : tst_shifts<"TSTxx", 0b1, i64, GPR64>;
+defm TSTww : tst_shifts<"TSTww", 0b0, i32, GPR32>;
-multiclass mvn_shifts<string prefix, bit sf, string sty, RegisterClass GPR>
-{
+multiclass mvn_shifts<string prefix, bit sf, ValueType ty, RegisterClass GPR> {
let isCommutable = 0, Rn = 0b11111 in {
def _lsl : A64I_logicalshift<sf, 0b01, 0b00, 0b1,
(outs GPR:$Rd),
(ins GPR:$Rm,
- !cast<Operand>("lsl_operand_" # sty):$Imm6),
+ !cast<Operand>("lsl_operand_" # ty):$Imm6),
"mvn\t$Rd, $Rm, $Imm6",
- [(set GPR:$Rd, (not (shl GPR:$Rm,
- !cast<Operand>("lsl_operand_" # sty):$Imm6)))],
+ [(set ty:$Rd, (not (shl ty:$Rm,
+ !cast<Operand>("lsl_operand_" # ty):$Imm6)))],
NoItinerary>;
def _lsr : A64I_logicalshift<sf, 0b01, 0b01, 0b1,
(outs GPR:$Rd),
(ins GPR:$Rm,
- !cast<Operand>("lsr_operand_" # sty):$Imm6),
+ !cast<Operand>("lsr_operand_" # ty):$Imm6),
"mvn\t$Rd, $Rm, $Imm6",
- [(set GPR:$Rd, (not (srl GPR:$Rm,
- !cast<Operand>("lsr_operand_" # sty):$Imm6)))],
+ [(set ty:$Rd, (not (srl ty:$Rm,
+ !cast<Operand>("lsr_operand_" # ty):$Imm6)))],
NoItinerary>;
def _asr : A64I_logicalshift<sf, 0b01, 0b10, 0b1,
(outs GPR:$Rd),
(ins GPR:$Rm,
- !cast<Operand>("asr_operand_" # sty):$Imm6),
+ !cast<Operand>("asr_operand_" # ty):$Imm6),
"mvn\t$Rd, $Rm, $Imm6",
- [(set GPR:$Rd, (not (sra GPR:$Rm,
- !cast<Operand>("asr_operand_" # sty):$Imm6)))],
+ [(set ty:$Rd, (not (sra ty:$Rm,
+ !cast<Operand>("asr_operand_" # ty):$Imm6)))],
NoItinerary>;
def _ror : A64I_logicalshift<sf, 0b01, 0b11, 0b1,
(outs GPR:$Rd),
(ins GPR:$Rm,
- !cast<Operand>("ror_operand_" # sty):$Imm6),
+ !cast<Operand>("ror_operand_" # ty):$Imm6),
"mvn\t$Rd, $Rm, $Imm6",
- [(set GPR:$Rd, (not (rotr GPR:$Rm,
- !cast<Operand>("lsl_operand_" # sty):$Imm6)))],
+ [(set ty:$Rd, (not (rotr ty:$Rm,
+ !cast<Operand>("lsl_operand_" # ty):$Imm6)))],
NoItinerary>;
}
def _noshift : InstAlias<"mvn $Rn, $Rm",
(!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
- def : Pat<(not GPR:$Rm),
- (!cast<Instruction>(prefix # "_lsl") GPR:$Rm, 0)>;
+ def : Pat<(not ty:$Rm),
+ (!cast<Instruction>(prefix # "_lsl") $Rm, 0)>;
}
-defm MVNxx : mvn_shifts<"MVNxx", 0b1, "i64", GPR64>;
-defm MVNww : mvn_shifts<"MVNww", 0b0, "i32", GPR32>;
+defm MVNxx : mvn_shifts<"MVNxx", 0b1, i64, GPR64>;
+defm MVNww : mvn_shifts<"MVNww", 0b0, i32, GPR32>;
def MOVxx :InstAlias<"mov $Rd, $Rm", (ORRxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>;
def MOVww :InstAlias<"mov $Rd, $Rm", (ORRwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>;
// A wide variety of different relocations are needed for variants of these
// instructions, so it turns out that we need a different operand for all of
// them.
-multiclass movw_operands<string prefix, string instname, int width>
-{
- def _imm_asmoperand : AsmOperandClass
- {
+multiclass movw_operands<string prefix, string instname, int width> {
+ def _imm_asmoperand : AsmOperandClass {
let Name = instname # width # "Shifted" # shift;
let PredicateMethod = "is" # instname # width # "Imm";
let RenderMethod = "addMoveWideImmOperands";
-
let ParserMethod = "ParseImmWithLSLOperand";
+ let DiagnosticType = "MOVWUImm16";
}
- def _imm : Operand<i32>
- {
+ def _imm : Operand<i64> {
let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_imm_asmoperand");
let PrintMethod = "printMoveWideImmOperand";
let EncoderMethod = "getMoveWideImmOpValue";
defm movk32 : movw_operands<"movk32", "MOVK", 32>;
defm movk64 : movw_operands<"movk64", "MOVK", 64>;
-multiclass A64I_movwSizes<bits<2> opc, string asmop, dag ins32bit, dag ins64bit>
-{
+multiclass A64I_movwSizes<bits<2> opc, string asmop, dag ins32bit,
+ dag ins64bit> {
def wii : A64I_movw<0b0, opc, (outs GPR32:$Rd), ins32bit,
!strconcat(asmop, "\t$Rd, $FullImm"),
- [], NoItinerary>
- {
+ [], NoItinerary> {
bits<18> FullImm;
let UImm16 = FullImm{15-0};
let Shift = FullImm{17-16};
def xii : A64I_movw<0b1, opc, (outs GPR64:$Rd), ins64bit,
!strconcat(asmop, "\t$Rd, $FullImm"),
- [], NoItinerary>
- {
+ [], NoItinerary> {
bits<18> FullImm;
let UImm16 = FullImm{15-0};
let Shift = FullImm{17-16};
}
let isMoveImm = 1, isReMaterializable = 1,
- isAsCheapAsAMove = 1, neverHasSideEffects = 1 in
-{
+ isAsCheapAsAMove = 1, hasSideEffects = 0 in {
defm MOVN : A64I_movwSizes<0b00, "movn",
(ins movn32_imm:$FullImm),
(ins movn64_imm:$FullImm)>;
// And now the "MOV" aliases. These also need their own operands because what
// they accept is completely different to what the base instructions accept.
multiclass movalias_operand<string prefix, string basename,
- string immpredicate, int width>
-{
- def _asmoperand : AsmOperandClass
- {
+ string immpredicate, int width> {
+ def _asmoperand : AsmOperandClass {
let Name = basename # width # "MovAlias";
let PredicateMethod
= "isMoveWideMovAlias<" # width # ", A64Imms::" # immpredicate # ">";
# "A64Imms::" # immpredicate # ">";
}
- def _movimm : Operand<i32>
- {
+ def _movimm : Operand<i64> {
let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift);
def : movalias<MOVNwii, GPR32, movn32_movimm>;
def : movalias<MOVNxii, GPR64, movn64_movimm>;
+def movw_addressref_g0 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<0>">;
+def movw_addressref_g1 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<1>">;
+def movw_addressref_g2 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<2>">;
+def movw_addressref_g3 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<3>">;
+
+def : Pat<(A64WrapperLarge movw_addressref_g3:$G3, movw_addressref_g2:$G2,
+ movw_addressref_g1:$G1, movw_addressref_g0:$G0),
+ (MOVKxii (MOVKxii (MOVKxii (MOVZxii movw_addressref_g3:$G3),
+ movw_addressref_g2:$G2),
+ movw_addressref_g1:$G1),
+ movw_addressref_g0:$G0)>;
+
//===----------------------------------------------------------------------===//
// PC-relative addressing instructions
//===----------------------------------------------------------------------===//
let OperandType = "OPERAND_PCREL";
}
-def adrp_label_asmoperand : AsmOperandClass
-{
+def adrp_label_asmoperand : AsmOperandClass {
let Name = "AdrpLabel";
let RenderMethod = "addLabelOperands<21, 4096>";
+ let DiagnosticType = "Label";
}
-def adrp_label : Operand<i64>
-{
+def adrp_label : Operand<i64> {
let EncoderMethod = "getAdrpLabelOpValue";
// This label is a 21-bit offset from PC, scaled by the page-size: 4096.
let OperandType = "OPERAND_PCREL";
}
-let neverHasSideEffects = 1 in
-{
+let hasSideEffects = 0 in {
def ADRxi : A64I_PCADR<0b0, (outs GPR64:$Rd), (ins adr_label:$Label),
"adr\t$Rd, $Label", [], NoItinerary>;
// + aliases IC, DC, AT, TLBI, NOP, YIELD, WFE, WFI, SEV, SEVL
// Op1 and Op2 fields are sometimes simple 3-bit unsigned immediate values.
-def uimm3_asmoperand : AsmOperandClass
-{
+def uimm3_asmoperand : AsmOperandClass {
let Name = "UImm3";
let PredicateMethod = "isUImm<3>";
let RenderMethod = "addImmOperands";
+ let DiagnosticType = "UImm3";
}
-def uimm3 : Operand<i32>
-{
+def uimm3 : Operand<i32> {
let ParserMatchClass = uimm3_asmoperand;
}
// The HINT alias can accept a simple unsigned 7-bit immediate.
-def uimm7_asmoperand : AsmOperandClass
-{
+def uimm7_asmoperand : AsmOperandClass {
let Name = "UImm7";
let PredicateMethod = "isUImm<7>";
let RenderMethod = "addImmOperands";
+ let DiagnosticType = "UImm7";
}
-def uimm7 : Operand<i32>
-{
+def uimm7 : Operand<i32> {
let ParserMatchClass = uimm7_asmoperand;
}
// * There are ~1000 generic names S3_<op1>_<CRn>_<CRm>_<Op2> which have an
// implementation-defined effect
// * Most registers are shared, but some are read-only or write-only.
-// * There is a variant of MSR which accepts the same register name (SPSel), but
-// which would have a different encoding.
+// * There is a variant of MSR which accepts the same register name (SPSel),
+// but which would have a different encoding.
// In principle these could be resolved in with more complicated subclasses of
// NamedImmMapper, however that imposes an overhead on other "named
// The solution adopted here is to take the MRS/MSR Mappers out of the usual
// hierarchy (they're not derived from NamedImmMapper) and to add logic for
// their special situation.
-def mrs_asmoperand : AsmOperandClass
-{
+def mrs_asmoperand : AsmOperandClass {
let Name = "MRS";
let ParserMethod = "ParseSysRegOperand";
+ let DiagnosticType = "MRS";
}
-def mrs_op : Operand<i32>
-{
+def mrs_op : Operand<i32> {
let ParserMatchClass = mrs_asmoperand;
let PrintMethod = "printMRSOperand";
let DecoderMethod = "DecodeMRSOperand";
}
-def msr_asmoperand : AsmOperandClass
-{
+def msr_asmoperand : AsmOperandClass {
let Name = "MSRWithReg";
// Note that SPSel is valid for both this and the pstate operands, but with
// AArch64Operand rather than an immediate. The overlap is small enough that
// it could be resolved with hackery now, but who can say in future?
let ParserMethod = "ParseSysRegOperand";
+ let DiagnosticType = "MSR";
}
-def msr_op : Operand<i32>
-{
+def msr_op : Operand<i32> {
let ParserMatchClass = msr_asmoperand;
let PrintMethod = "printMSROperand";
let DecoderMethod = "DecodeMSROperand";
}
-def pstate_asmoperand : AsmOperandClass
-{
+def pstate_asmoperand : AsmOperandClass {
let Name = "MSRPState";
// See comment above about parser.
let ParserMethod = "ParseSysRegOperand";
+ let DiagnosticType = "MSR";
}
-def pstate_op : Operand<i32>
-{
+def pstate_op : Operand<i32> {
let ParserMatchClass = pstate_asmoperand;
let PrintMethod = "printNamedImmOperand<A64PState::PStateMapper>";
let DecoderMethod = "DecodeNamedImmOperand<A64PState::PStateMapper>";
// When <CRn> is specified, an assembler should accept something like "C4", not
// the usual "#4" immediate.
-def CRx_asmoperand : AsmOperandClass
-{
+def CRx_asmoperand : AsmOperandClass {
let Name = "CRx";
let PredicateMethod = "isUImm<4>";
let RenderMethod = "addImmOperands";
let ParserMethod = "ParseCRxOperand";
+ // Diagnostics are handled in all cases by ParseCRxOperand.
}
-def CRx : Operand<i32>
-{
+def CRx : Operand<i32> {
let ParserMatchClass = CRx_asmoperand;
let PrintMethod = "printCRxOperand";
}
// HINT is straightforward, with a few aliases.
def HINTi : A64I_system<0b0, (outs), (ins uimm7:$UImm7), "hint\t$UImm7",
- [], NoItinerary>
-{
+ [], NoItinerary> {
bits<7> UImm7;
let CRm = UImm7{6-3};
let Op2 = UImm7{2-0};
class simple_sys<bits<2> op0, bits<3> op1, bits<4> crn, bits<3> op2,
Operand operand, string asmop>
: A64I_system<0b0, (outs), (ins operand:$CRm), !strconcat(asmop, "\t$CRm"),
- [], NoItinerary>
-{
+ [], NoItinerary> {
let Op0 = op0;
let Op1 = op1;
let CRn = crn;
(ins uimm3:$Op1, CRx:$CRn, CRx:$CRm,
uimm3:$Op2, GPR64:$Rt),
"sys\t$Op1, $CRn, $CRm, $Op2, $Rt",
- [], NoItinerary>
-{
+ [], NoItinerary> {
let Op0 = 0b01;
}
// But many have aliases, which obviously don't fit into
class SYSalias<dag ins, string asmstring>
- : A64I_system<0b0, (outs), ins, asmstring, [], NoItinerary>
-{
+ : A64I_system<0b0, (outs), ins, asmstring, [], NoItinerary> {
let isAsmParserOnly = 1;
bits<14> SysOp;
def ICix : SYSalias<(ins ic_op:$SysOp, GPR64:$Rt), "ic\t$SysOp, $Rt">;
-def ICi : SYSalias<(ins ic_op:$SysOp), "ic\t$SysOp">
-{
+def ICi : SYSalias<(ins ic_op:$SysOp), "ic\t$SysOp"> {
let Rt = 0b11111;
}
def TLBIix : SYSalias<(ins tlbi_op:$SysOp, GPR64:$Rt), "tlbi\t$SysOp, $Rt">;
-def TLBIi : SYSalias<(ins tlbi_op:$SysOp), "tlbi\t$SysOp">
-{
+def TLBIi : SYSalias<(ins tlbi_op:$SysOp), "tlbi\t$SysOp"> {
let Rt = 0b11111;
}
def SYSLxicci : A64I_system<0b1, (outs GPR64:$Rt),
(ins uimm3:$Op1, CRx:$CRn, CRx:$CRm, uimm3:$Op2),
"sysl\t$Rt, $Op1, $CRn, $CRm, $Op2",
- [], NoItinerary>
-{
+ [], NoItinerary> {
let Op0 = 0b01;
}
// The instructions themselves are rather simple for MSR and MRS.
def MSRix : A64I_system<0b0, (outs), (ins msr_op:$SysReg, GPR64:$Rt),
- "msr\t$SysReg, $Rt", [], NoItinerary>
-{
+ "msr\t$SysReg, $Rt", [], NoItinerary> {
bits<16> SysReg;
let Op0 = SysReg{15-14};
let Op1 = SysReg{13-11};
}
def MRSxi : A64I_system<0b1, (outs GPR64:$Rt), (ins mrs_op:$SysReg),
- "mrs\t$Rt, $SysReg", [], NoItinerary>
-{
+ "mrs\t$Rt, $SysReg", [], NoItinerary> {
bits<16> SysReg;
let Op0 = SysReg{15-14};
let Op1 = SysReg{13-11};
}
def MSRii : A64I_system<0b0, (outs), (ins pstate_op:$PState, uimm4:$CRm),
- "msr\t$PState, $CRm", [], NoItinerary>
-{
+ "msr\t$PState, $CRm", [], NoItinerary> {
bits<6> PState;
let Op0 = 0b00;
// The bit to test is a simple unsigned 6-bit immediate in the X-register
// versions.
-def uimm6 : Operand<i64>
-{
+def uimm6 : Operand<i64> {
let ParserMatchClass = uimm6_asmoperand;
}
def label_wid14_scal4_asmoperand : label_asmoperand<14, 4>;
-def tbimm_target : Operand<OtherVT>
-{
+def tbimm_target : Operand<OtherVT> {
let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_tstbr>";
// This label is a 14-bit offset from PC, scaled by the instruction-width: 4.
def tstb64_pat : ComplexPattern<i64, 1, "SelectTSTBOperand<64>">;
def tstb32_pat : ComplexPattern<i32, 1, "SelectTSTBOperand<32>">;
-let isBranch = 1, isTerminator = 1 in
-{
+let isBranch = 1, isTerminator = 1 in {
def TBZxii : A64I_TBimm<0b0, (outs),
(ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label),
"tbz\t$Rt, $Imm, $Label",
- [(A64br_cc (A64cmp (and GPR64:$Rt, tstb64_pat:$Imm), 0),
+ [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0),
A64eq, bb:$Label)],
NoItinerary>;
def TBNZxii : A64I_TBimm<0b1, (outs),
(ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label),
"tbnz\t$Rt, $Imm, $Label",
- [(A64br_cc (A64cmp (and GPR64:$Rt, tstb64_pat:$Imm), 0),
+ [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0),
A64ne, bb:$Label)],
NoItinerary>;
def TBZwii : A64I_TBimm<0b0, (outs),
(ins GPR32:$Rt, uimm5:$Imm, tbimm_target:$Label),
"tbz\t$Rt, $Imm, $Label",
- [(A64br_cc (A64cmp (and GPR32:$Rt, tstb32_pat:$Imm), 0),
+ [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0),
A64eq, bb:$Label)],
- NoItinerary>
- {
+ NoItinerary> {
let Imm{5} = 0b0;
}
def TBNZwii : A64I_TBimm<0b1, (outs),
(ins GPR32:$Rt, uimm5:$Imm, tbimm_target:$Label),
"tbnz\t$Rt, $Imm, $Label",
- [(A64br_cc (A64cmp (and GPR32:$Rt, tstb32_pat:$Imm), 0),
+ [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0),
A64ne, bb:$Label)],
- NoItinerary>
- {
+ NoItinerary> {
let Imm{5} = 0b0;
}
}
def label_wid26_scal4_asmoperand : label_asmoperand<26, 4>;
-def bimm_target : Operand<OtherVT>
-{
+def bimm_target : Operand<OtherVT> {
let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_uncondbr>";
// This label is a 26-bit offset from PC, scaled by the instruction-width: 4.
let OperandType = "OPERAND_PCREL";
}
-def blimm_target : Operand<i64>
-{
+def blimm_target : Operand<i64> {
let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_call>";
// This label is a 26-bit offset from PC, scaled by the instruction-width: 4.
NoItinerary>;
let isBranch = 1 in {
- def Bimm : A64I_BimmImpl<0b0, "b", [(br bb:$Label)], bimm_target>
- {
+ def Bimm : A64I_BimmImpl<0b0, "b", [(br bb:$Label)], bimm_target> {
let isTerminator = 1;
let isBarrier = 1;
}
def BLimm : A64I_BimmImpl<0b1, "bl",
- [(AArch64Call tglobaladdr:$Label)], blimm_target>
- {
+ [(AArch64Call tglobaladdr:$Label)], blimm_target> {
let isCall = 1;
let Defs = [X30];
}
dag outs, dag ins, string asmstr, list<dag> patterns,
InstrItinClass itin = NoItinerary>
: A64I_Breg<opc, 0b11111, 0b000000, 0b00000,
- outs, ins, asmstr, patterns, itin>
-{
+ outs, ins, asmstr, patterns, itin> {
let isBranch = 1;
let isIndirectBranch = 1;
}
let isBranch = 1 in {
def BRx : A64I_BregImpl<0b0000,(outs), (ins GPR64:$Rn),
- "br\t$Rn", [(brind GPR64:$Rn)]>
- {
+ "br\t$Rn", [(brind i64:$Rn)]> {
let isBarrier = 1;
let isTerminator = 1;
}
def BLRx : A64I_BregImpl<0b0001, (outs), (ins GPR64:$Rn),
- "blr\t$Rn", [(AArch64Call GPR64:$Rn)]>
- {
+ "blr\t$Rn", [(AArch64Call i64:$Rn)]> {
let isBarrier = 0;
let isCall = 1;
let Defs = [X30];
}
def RETx : A64I_BregImpl<0b0010, (outs), (ins GPR64:$Rn),
- "ret\t$Rn", []>
- {
+ "ret\t$Rn", []> {
let isBarrier = 1;
let isTerminator = 1;
let isReturn = 1;
// Create a separate pseudo-instruction for codegen to use so that we don't
// flag x30 as used in every function. It'll be restored before the RET by the
// epilogue if it's legitimately used.
- def RET : A64PseudoExpand<(outs), (ins), [(A64ret)], (RETx (ops X30))>
- {
+ def RET : A64PseudoExpand<(outs), (ins), [(A64ret)], (RETx (ops X30))> {
let isTerminator = 1;
let isBarrier = 1;
let isReturn = 1;
}
- def ERET : A64I_BregImpl<0b0100, (outs), (ins), "eret", []>
- {
+ def ERET : A64I_BregImpl<0b0100, (outs), (ins), "eret", []> {
let Rn = 0b11111;
let isBarrier = 1;
let isTerminator = 1;
let isReturn = 1;
}
- def DRPS : A64I_BregImpl<0b0101, (outs), (ins), "drps", []>
- {
+ def DRPS : A64I_BregImpl<0b0101, (outs), (ins), "drps", []> {
let Rn = 0b11111;
let isBarrier = 1;
}
// GOT access patterns
//===----------------------------------------------------------------------===//
-// FIXME: Wibble
-
class GOTLoadSmall<SDNode addrfrag>
: Pat<(A64GOTLoad (A64WrapperSmall addrfrag:$Hi, addrfrag:$Lo12, 8)),
(LS64_LDR (ADRPxi addrfrag:$Hi), addrfrag:$Lo12)>;
// Tail call handling
//===----------------------------------------------------------------------===//
-let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [XSP] in
-{
+let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [XSP] in {
def TC_RETURNdi
: PseudoInst<(outs), (ins i64imm:$dst, i32imm:$FPDiff),
[(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff))]>;
def TC_RETURNxi
: PseudoInst<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff),
- [(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff))]>;
+ [(AArch64tcret i64:$dst, (i32 timm:$FPDiff))]>;
}
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
- Uses = [XSP] in
-{
+ Uses = [XSP] in {
def TAIL_Bimm : A64PseudoExpand<(outs), (ins bimm_target:$Label), [],
(Bimm bimm_target:$Label)>;
def : Pat<(A64threadpointer), (MRSxi 0xde82)>;
-def TLSDESCCALL : PseudoInst<(outs), (ins i64imm:$Lbl), []>
-{
+def TLSDESCCALL : PseudoInst<(outs), (ins i64imm:$Lbl), []> {
let hasSideEffects = 1;
}
def TLSDESC_BLRx : PseudoInst<(outs), (ins GPR64:$Rn, i64imm:$Var),
- [(A64tlsdesc_blr GPR64:$Rn, tglobaltlsaddr:$Var)]>
-{
+ [(A64tlsdesc_blr i64:$Rn, tglobaltlsaddr:$Var)]> {
let isCall = 1;
let Defs = [X30];
}
-def : Pat<(A64tlsdesc_blr GPR64:$Rn, texternalsym:$Var),
- (TLSDESC_BLRx GPR64:$Rn, texternalsym:$Var)>;
+def : Pat<(A64tlsdesc_blr i64:$Rn, texternalsym:$Var),
+ (TLSDESC_BLRx $Rn, texternalsym:$Var)>;
//===----------------------------------------------------------------------===//
// Bitfield patterns
// (either all bits are used or the low 32 bits are used).
let AddedComplexity = 10 in {
-def : Pat<(A64Bfi GPR64:$src, GPR64:$Rn, imm:$ImmR, imm:$ImmS),
- (BFIxxii GPR64:$src, GPR64:$Rn,
+def : Pat<(A64Bfi i64:$src, i64:$Rn, imm:$ImmR, imm:$ImmS),
+ (BFIxxii $src, $Rn,
(bfi64_lsb_to_immr (i64 imm:$ImmR)),
(bfi_width_to_imms (i64 imm:$ImmS)))>;
-def : Pat<(A64Bfi GPR32:$src, GPR32:$Rn, imm:$ImmR, imm:$ImmS),
- (BFIwwii GPR32:$src, GPR32:$Rn,
+def : Pat<(A64Bfi i32:$src, i32:$Rn, imm:$ImmR, imm:$ImmS),
+ (BFIwwii $src, $Rn,
(bfi32_lsb_to_immr (i64 imm:$ImmR)),
(bfi_width_to_imms (i64 imm:$ImmS)))>;
-def : Pat<(and (A64Bfi GPR64:$src, GPR64:$Rn, imm:$ImmR, imm:$ImmS),
+def : Pat<(and (A64Bfi i64:$src, i64:$Rn, imm:$ImmR, imm:$ImmS),
(i64 4294967295)),
(SUBREG_TO_REG (i64 0),
- (BFIwwii (EXTRACT_SUBREG GPR64:$src, sub_32),
- (EXTRACT_SUBREG GPR64:$Rn, sub_32),
+ (BFIwwii (EXTRACT_SUBREG $src, sub_32),
+ (EXTRACT_SUBREG $Rn, sub_32),
(bfi32_lsb_to_immr (i64 imm:$ImmR)),
(bfi_width_to_imms (i64 imm:$ImmS))),
sub_32)>;
}
-//===----------------------------------------------------------------------===//
-// Constant island entries
-//===----------------------------------------------------------------------===//
-
-// The constant island pass needs to create "instructions" in the middle of the
-// instruction stream to reresent its constants.
-
-def cpinst_operand : Operand<i32>;
-
-def CONSTPOOL_ENTRY : PseudoInst<(outs), (ins cpinst_operand:$instid,
- cpinst_operand:$cpidx,
- i32imm:$size), []>
-{
- let neverHasSideEffects = 1;
- let isNotDuplicable = 1;
-}
-
//===----------------------------------------------------------------------===//
// Miscellaneous patterns
//===----------------------------------------------------------------------===//
// Truncation from 64 to 32-bits just involves renaming your register.
-def : Pat<(i32 (trunc (i64 GPR64:$val))), (EXTRACT_SUBREG GPR64:$val, sub_32)>;
+def : Pat<(i32 (trunc i64:$val)), (EXTRACT_SUBREG $val, sub_32)>;
// Similarly, extension where we don't care about the high bits is
// just a rename.
-def : Pat<(i64 (anyext (i32 GPR32:$val))),
- (INSERT_SUBREG (IMPLICIT_DEF), GPR32:$val, sub_32)>;
+def : Pat<(i64 (anyext i32:$val)),
+ (INSERT_SUBREG (IMPLICIT_DEF), $val, sub_32)>;
// SELECT instructions providing f128 types need to be handled by a
// pseudo-instruction since the eventual code will need to introduce basic
// blocks and control flow.
def F128CSEL : PseudoInst<(outs FPR128:$Rd),
- (ins FPR128:$Rn, FPR128:$Rm, cond_code_op:$Cond),
- [(set FPR128:$Rd, (simple_select (f128 FPR128:$Rn),
- FPR128:$Rm))]>
-{
+ (ins FPR128:$Rn, FPR128:$Rm, cond_code_op:$Cond),
+ [(set f128:$Rd, (simple_select f128:$Rn, f128:$Rm))]> {
let Uses = [NZCV];
let usesCustomInserter = 1;
}
//===------------------------------
// First, some simple classes for !foreach and !subst to use:
-class Decls
-{
+class Decls {
dag pattern;
}
// Atomic patterns can be shared between integer operations of all sizes, a
// quick multiclass here allows reuse.
multiclass ls_atomic_pats<Instruction LOAD, Instruction STORE, dag Base,
- dag Offset, dag address, RegisterClass TPR,
- ValueType sty>
-{
+ dag Offset, dag address, ValueType transty,
+ ValueType sty> {
def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address),
(LOAD Base, Offset)>;
- def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, TPR:$Rt),
- (STORE TPR:$Rt, Base, Offset)>;
+ def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, transty:$Rt),
+ (STORE $Rt, Base, Offset)>;
}
// Instructions accessing a memory chunk smaller than a register (or, in a
multiclass ls_small_pats<Instruction LOAD, Instruction STORE,
dag Base, dag Offset,
dag address, ValueType sty>
- : ls_atomic_pats<LOAD, STORE, Base, Offset, address, GPR32, sty>
-{
+ : ls_atomic_pats<LOAD, STORE, Base, Offset, address, i32, sty> {
def : Pat<(!cast<SDNode>(zextload # sty) address), (LOAD Base, Offset)>;
def : Pat<(!cast<SDNode>(extload # sty) address), (LOAD Base, Offset)>;
def : Pat<(i64 (!cast<SDNode>(extload # sty) address)),
(SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>;
- def : Pat<(!cast<SDNode>(truncstore # sty) GPR32:$Rt, address),
- (STORE GPR32:$Rt, Base, Offset)>;
+ def : Pat<(!cast<SDNode>(truncstore # sty) i32:$Rt, address),
+ (STORE $Rt, Base, Offset)>;
// For truncating store from 64-bits, we have to manually tell LLVM to
// ignore the high bits of the x register.
- def : Pat<(!cast<SDNode>(truncstore # sty) GPR64:$Rt, address),
- (STORE (EXTRACT_SUBREG GPR64:$Rt, sub_32), Base, Offset)>;
+ def : Pat<(!cast<SDNode>(truncstore # sty) i64:$Rt, address),
+ (STORE (EXTRACT_SUBREG $Rt, sub_32), Base, Offset)>;
}
// Next come patterns for sign-extending loads.
multiclass load_signed_pats<string T, string U, dag Base, dag Offset,
- dag address, ValueType sty>
-{
+ dag address, ValueType sty> {
def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)),
(!cast<Instruction>("LDRS" # T # "w" # U) Base, Offset)>;
// and finally "natural-width" loads and stores come next.
multiclass ls_neutral_pats<Instruction LOAD, Instruction STORE, dag Base,
- dag Offset, dag address, RegisterClass TPR,
- ValueType sty>
-{
+ dag Offset, dag address, ValueType sty> {
def : Pat<(sty (load address)), (LOAD Base, Offset)>;
- def : Pat<(store (sty TPR:$Rt), address), (STORE TPR:$Rt, Base, Offset)>;
+ def : Pat<(store sty:$Rt, address), (STORE $Rt, Base, Offset)>;
}
// Integer operations also get atomic instructions to select for.
multiclass ls_int_neutral_pats<Instruction LOAD, Instruction STORE, dag Base,
- dag Offset, dag address, RegisterClass TPR,
- ValueType sty>
- : ls_neutral_pats<LOAD, STORE, Base, Offset, address, TPR, sty>,
- ls_atomic_pats<LOAD, STORE, Base, Offset, address, TPR, sty>;
+ dag Offset, dag address, ValueType sty>
+ : ls_neutral_pats<LOAD, STORE, Base, Offset, address, sty>,
+ ls_atomic_pats<LOAD, STORE, Base, Offset, address, sty, sty>;
//===------------------------------
// 2.2. Addressing-mode instantiations
//===------------------------------
-multiclass uimm12_pats<dag address, dag Base, dag Offset>
-{
+multiclass uimm12_pats<dag address, dag Base, dag Offset> {
defm : ls_small_pats<LS8_LDR, LS8_STR, Base,
!foreach(decls.pattern, Offset,
!subst(OFFSET, byte_uimm12, decls.pattern)),
!foreach(decls.pattern, address,
!subst(OFFSET, word_uimm12,
!subst(ALIGN, min_align4, decls.pattern))),
- GPR32, i32>;
+ i32>;
defm : ls_int_neutral_pats<LS64_LDR, LS64_STR, Base,
!foreach(decls.pattern, Offset,
!foreach(decls.pattern, address,
!subst(OFFSET, dword_uimm12,
!subst(ALIGN, min_align8, decls.pattern))),
- GPR64, i64>;
+ i64>;
defm : ls_neutral_pats<LSFP16_LDR, LSFP16_STR, Base,
!foreach(decls.pattern, Offset,
!foreach(decls.pattern, address,
!subst(OFFSET, hword_uimm12,
!subst(ALIGN, min_align2, decls.pattern))),
- FPR16, f16>;
+ f16>;
defm : ls_neutral_pats<LSFP32_LDR, LSFP32_STR, Base,
!foreach(decls.pattern, Offset,
!foreach(decls.pattern, address,
!subst(OFFSET, word_uimm12,
!subst(ALIGN, min_align4, decls.pattern))),
- FPR32, f32>;
+ f32>;
defm : ls_neutral_pats<LSFP64_LDR, LSFP64_STR, Base,
!foreach(decls.pattern, Offset,
!foreach(decls.pattern, address,
!subst(OFFSET, dword_uimm12,
!subst(ALIGN, min_align8, decls.pattern))),
- FPR64, f64>;
+ f64>;
defm : ls_neutral_pats<LSFP128_LDR, LSFP128_STR, Base,
!foreach(decls.pattern, Offset,
!foreach(decls.pattern, address,
!subst(OFFSET, qword_uimm12,
!subst(ALIGN, min_align16, decls.pattern))),
- FPR128, f128>;
+ f128>;
defm : load_signed_pats<"B", "", Base,
!foreach(decls.pattern, Offset,
!subst(OFFSET, word_uimm12,
!subst(ALIGN, min_align4, decls.pattern)))),
(LDRSWx Base, !foreach(decls.pattern, Offset,
- !subst(OFFSET, word_uimm12, decls.pattern)))>;
+ !subst(OFFSET, word_uimm12, decls.pattern)))>;
}
// Straightforward patterns of last resort: a pointer with or without an
// appropriate offset.
-defm : uimm12_pats<(i64 GPR64xsp:$Rn), (i64 GPR64xsp:$Rn), (i64 0)>;
-defm : uimm12_pats<(add GPR64xsp:$Rn, OFFSET:$UImm12),
- (i64 GPR64xsp:$Rn), (i64 OFFSET:$UImm12)>;
+defm : uimm12_pats<(i64 i64:$Rn), (i64 i64:$Rn), (i64 0)>;
+defm : uimm12_pats<(add i64:$Rn, OFFSET:$UImm12),
+ (i64 i64:$Rn), (i64 OFFSET:$UImm12)>;
// The offset could be hidden behind an "or", of course:
-defm : uimm12_pats<(add_like_or GPR64xsp:$Rn, OFFSET:$UImm12),
- (i64 GPR64xsp:$Rn), (i64 OFFSET:$UImm12)>;
+defm : uimm12_pats<(add_like_or i64:$Rn, OFFSET:$UImm12),
+ (i64 i64:$Rn), (i64 OFFSET:$UImm12)>;
// Global addresses under the small-absolute model should use these
// instructions. There are ELF relocations specifically for it.
defm : uimm12_pats<(A64WrapperSmall tglobaladdr:$Hi, tglobaladdr:$Lo12, ALIGN),
(ADRPxi tglobaladdr:$Hi), (i64 tglobaladdr:$Lo12)>;
-defm : uimm12_pats<(A64WrapperSmall tglobaltlsaddr:$Hi, tglobaltlsaddr:$Lo12, ALIGN),
+defm : uimm12_pats<(A64WrapperSmall tglobaltlsaddr:$Hi, tglobaltlsaddr:$Lo12,
+ ALIGN),
(ADRPxi tglobaltlsaddr:$Hi), (i64 tglobaltlsaddr:$Lo12)>;
// External symbols that make it this far should also get standard relocations.
-defm : uimm12_pats<(A64WrapperSmall texternalsym:$Hi, texternalsym:$Lo12, ALIGN),
+defm : uimm12_pats<(A64WrapperSmall texternalsym:$Hi, texternalsym:$Lo12,
+ ALIGN),
(ADRPxi texternalsym:$Hi), (i64 texternalsym:$Lo12)>;
+defm : uimm12_pats<(A64WrapperSmall tconstpool:$Hi, tconstpool:$Lo12, ALIGN),
+ (ADRPxi tconstpool:$Hi), (i64 tconstpool:$Lo12)>;
// We also want to use uimm12 instructions for local variables at the moment.
def tframeindex_XFORM : SDNodeXForm<frameindex, [{
// These can be much simpler than uimm12 because we don't to change the operand
// type (e.g. LDURB and LDURH take the same operands).
-multiclass simm9_pats<dag address, dag Base, dag Offset>
-{
+multiclass simm9_pats<dag address, dag Base, dag Offset> {
defm : ls_small_pats<LS8_LDUR, LS8_STUR, Base, Offset, address, i8>;
defm : ls_small_pats<LS16_LDUR, LS16_STUR, Base, Offset, address, i16>;
- defm : ls_int_neutral_pats<LS32_LDUR, LS32_STUR, Base, Offset, address,
- GPR32, i32>;
- defm : ls_int_neutral_pats<LS64_LDUR, LS64_STUR, Base, Offset, address,
- GPR64, i64>;
-
- defm : ls_neutral_pats<LSFP16_LDUR, LSFP16_STUR, Base, Offset, address,
- FPR16, f16>;
- defm : ls_neutral_pats<LSFP32_LDUR, LSFP32_STUR, Base, Offset, address,
- FPR32, f32>;
- defm : ls_neutral_pats<LSFP64_LDUR, LSFP64_STUR, Base, Offset, address,
- FPR64, f64>;
+ defm : ls_int_neutral_pats<LS32_LDUR, LS32_STUR, Base, Offset, address, i32>;
+ defm : ls_int_neutral_pats<LS64_LDUR, LS64_STUR, Base, Offset, address, i64>;
+
+ defm : ls_neutral_pats<LSFP16_LDUR, LSFP16_STUR, Base, Offset, address, f16>;
+ defm : ls_neutral_pats<LSFP32_LDUR, LSFP32_STUR, Base, Offset, address, f32>;
+ defm : ls_neutral_pats<LSFP64_LDUR, LSFP64_STUR, Base, Offset, address, f64>;
defm : ls_neutral_pats<LSFP128_LDUR, LSFP128_STUR, Base, Offset, address,
- FPR128, f128>;
+ f128>;
def : Pat<(i64 (zextloadi32 address)),
(SUBREG_TO_REG (i64 0), (LS32_LDUR Base, Offset), sub_32)>;
- def : Pat<(truncstorei32 GPR64:$Rt, address),
- (LS32_STUR (EXTRACT_SUBREG GPR64:$Rt, sub_32), Base, Offset)>;
+ def : Pat<(truncstorei32 i64:$Rt, address),
+ (LS32_STUR (EXTRACT_SUBREG $Rt, sub_32), Base, Offset)>;
defm : load_signed_pats<"B", "_U", Base, Offset, address, i8>;
defm : load_signed_pats<"H", "_U", Base, Offset, address, i16>;
def : Pat<(sextloadi32 address), (LDURSWx Base, Offset)>;
}
-defm : simm9_pats<(add GPR64xsp:$Rn, simm9:$SImm9),
- (i64 GPR64xsp:$Rn), (SDXF_simm9 simm9:$SImm9)>;
+defm : simm9_pats<(add i64:$Rn, simm9:$SImm9),
+ (i64 $Rn), (SDXF_simm9 simm9:$SImm9)>;
-defm : simm9_pats<(add_like_or GPR64xsp:$Rn, simm9:$SImm9),
- (i64 GPR64xsp:$Rn), (SDXF_simm9 simm9:$SImm9)>;
+defm : simm9_pats<(add_like_or i64:$Rn, simm9:$SImm9),
+ (i64 $Rn), (SDXF_simm9 simm9:$SImm9)>;
//===------------------------------
// quick multiclass here allows reuse.
multiclass ro_atomic_pats<Instruction LOAD, Instruction STORE, dag Base,
dag Offset, dag Extend, dag address,
- RegisterClass TPR, ValueType sty>
-{
+ ValueType transty, ValueType sty> {
def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address),
(LOAD Base, Offset, Extend)>;
- def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, TPR:$Rt),
- (STORE TPR:$Rt, Base, Offset, Extend)>;
+ def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, transty:$Rt),
+ (STORE $Rt, Base, Offset, Extend)>;
}
// The register offset instructions take three operands giving the instruction,
multiclass ro_small_pats<Instruction LOAD, Instruction STORE,
dag Base, dag Offset, dag Extend,
dag address, ValueType sty>
- : ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, GPR32, sty>
-{
+ : ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, i32, sty> {
def : Pat<(!cast<SDNode>(zextload # sty) address),
(LOAD Base, Offset, Extend)>;
def : Pat<(i64 (!cast<SDNode>(extload # sty) address)),
(SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>;
- def : Pat<(!cast<SDNode>(truncstore # sty) GPR32:$Rt, address),
- (STORE GPR32:$Rt, Base, Offset, Extend)>;
+ def : Pat<(!cast<SDNode>(truncstore # sty) i32:$Rt, address),
+ (STORE $Rt, Base, Offset, Extend)>;
// For truncating store from 64-bits, we have to manually tell LLVM to
// ignore the high bits of the x register.
- def : Pat<(!cast<SDNode>(truncstore # sty) GPR64:$Rt, address),
- (STORE (EXTRACT_SUBREG GPR64:$Rt, sub_32), Base, Offset, Extend)>;
+ def : Pat<(!cast<SDNode>(truncstore # sty) i64:$Rt, address),
+ (STORE (EXTRACT_SUBREG $Rt, sub_32), Base, Offset, Extend)>;
}
// Next come patterns for sign-extending loads.
multiclass ro_signed_pats<string T, string Rm, dag Base, dag Offset, dag Extend,
- dag address, ValueType sty>
-{
+ dag address, ValueType sty> {
def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)),
(!cast<Instruction>("LDRS" # T # "w_" # Rm # "_RegOffset")
Base, Offset, Extend)>;
// and finally "natural-width" loads and stores come next.
multiclass ro_neutral_pats<Instruction LOAD, Instruction STORE,
dag Base, dag Offset, dag Extend, dag address,
- RegisterClass TPR, ValueType sty>
-{
+ ValueType sty> {
def : Pat<(sty (load address)), (LOAD Base, Offset, Extend)>;
- def : Pat<(store (sty TPR:$Rt), address),
- (STORE TPR:$Rt, Base, Offset, Extend)>;
+ def : Pat<(store sty:$Rt, address),
+ (STORE $Rt, Base, Offset, Extend)>;
}
multiclass ro_int_neutral_pats<Instruction LOAD, Instruction STORE,
- dag Base, dag Offset, dag Extend, dag address,
- RegisterClass TPR, ValueType sty>
- : ro_neutral_pats<LOAD, STORE, Base, Offset, Extend, address, TPR, sty>,
- ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, TPR, sty>;
+ dag Base, dag Offset, dag Extend, dag address,
+ ValueType sty>
+ : ro_neutral_pats<LOAD, STORE, Base, Offset, Extend, address, sty>,
+ ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, sty, sty>;
-multiclass regoff_pats<string Rm, dag address, dag Base, dag Offset, dag Extend>
-{
+multiclass regoff_pats<string Rm, dag address, dag Base, dag Offset,
+ dag Extend> {
defm : ro_small_pats<!cast<Instruction>("LS8_" # Rm # "_RegOffset_LDR"),
!cast<Instruction>("LS8_" # Rm # "_RegOffset_STR"),
Base, Offset, Extend,
!subst(SHIFT, imm_eq2, decls.pattern)),
i32>;
- defm : ro_int_neutral_pats<!cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"),
- !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"),
- Base, Offset, Extend,
- !foreach(decls.pattern, address,
- !subst(SHIFT, imm_eq2, decls.pattern)),
- GPR32, i32>;
-
- defm : ro_int_neutral_pats<!cast<Instruction>("LS64_" # Rm # "_RegOffset_LDR"),
- !cast<Instruction>("LS64_" # Rm # "_RegOffset_STR"),
- Base, Offset, Extend,
- !foreach(decls.pattern, address,
- !subst(SHIFT, imm_eq3, decls.pattern)),
- GPR64, i64>;
+ defm : ro_int_neutral_pats<
+ !cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"),
+ !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"),
+ Base, Offset, Extend,
+ !foreach(decls.pattern, address,
+ !subst(SHIFT, imm_eq2, decls.pattern)),
+ i32>;
+
+ defm : ro_int_neutral_pats<
+ !cast<Instruction>("LS64_" # Rm # "_RegOffset_LDR"),
+ !cast<Instruction>("LS64_" # Rm # "_RegOffset_STR"),
+ Base, Offset, Extend,
+ !foreach(decls.pattern, address,
+ !subst(SHIFT, imm_eq3, decls.pattern)),
+ i64>;
defm : ro_neutral_pats<!cast<Instruction>("LSFP16_" # Rm # "_RegOffset_LDR"),
!cast<Instruction>("LSFP16_" # Rm # "_RegOffset_STR"),
Base, Offset, Extend,
!foreach(decls.pattern, address,
!subst(SHIFT, imm_eq1, decls.pattern)),
- FPR16, f16>;
+ f16>;
defm : ro_neutral_pats<!cast<Instruction>("LSFP32_" # Rm # "_RegOffset_LDR"),
!cast<Instruction>("LSFP32_" # Rm # "_RegOffset_STR"),
Base, Offset, Extend,
!foreach(decls.pattern, address,
!subst(SHIFT, imm_eq2, decls.pattern)),
- FPR32, f32>;
+ f32>;
defm : ro_neutral_pats<!cast<Instruction>("LSFP64_" # Rm # "_RegOffset_LDR"),
!cast<Instruction>("LSFP64_" # Rm # "_RegOffset_STR"),
Base, Offset, Extend,
!foreach(decls.pattern, address,
!subst(SHIFT, imm_eq3, decls.pattern)),
- FPR64, f64>;
+ f64>;
defm : ro_neutral_pats<!cast<Instruction>("LSFP128_" # Rm # "_RegOffset_LDR"),
!cast<Instruction>("LSFP128_" # Rm # "_RegOffset_STR"),
Base, Offset, Extend,
!foreach(decls.pattern, address,
!subst(SHIFT, imm_eq4, decls.pattern)),
- FPR128, f128>;
+ f128>;
defm : ro_signed_pats<"B", Rm, Base, Offset, Extend,
- !foreach(decls.pattern, address,
- !subst(SHIFT, imm_eq0, decls.pattern)),
- i8>;
+ !foreach(decls.pattern, address,
+ !subst(SHIFT, imm_eq0, decls.pattern)),
+ i8>;
defm : ro_signed_pats<"H", Rm, Base, Offset, Extend,
- !foreach(decls.pattern, address,
- !subst(SHIFT, imm_eq1, decls.pattern)),
- i16>;
+ !foreach(decls.pattern, address,
+ !subst(SHIFT, imm_eq1, decls.pattern)),
+ i16>;
def : Pat<(sextloadi32 !foreach(decls.pattern, address,
!subst(SHIFT, imm_eq2, decls.pattern))),
// using register-offset instructions. Essentially a base plus a possibly
// extended, possibly shifted (by access size) offset.
-defm : regoff_pats<"Wm", (add GPR64xsp:$Rn, (sext GPR32:$Rm)),
- (i64 GPR64xsp:$Rn), (i32 GPR32:$Rm), (i64 6)>;
+defm : regoff_pats<"Wm", (add i64:$Rn, (sext i32:$Rm)),
+ (i64 i64:$Rn), (i32 i32:$Rm), (i64 6)>;
+
+defm : regoff_pats<"Wm", (add i64:$Rn, (shl (sext i32:$Rm), SHIFT)),
+ (i64 i64:$Rn), (i32 i32:$Rm), (i64 7)>;
+
+defm : regoff_pats<"Wm", (add i64:$Rn, (zext i32:$Rm)),
+ (i64 i64:$Rn), (i32 i32:$Rm), (i64 2)>;
-defm : regoff_pats<"Wm", (add GPR64xsp:$Rn, (shl (sext GPR32:$Rm), SHIFT)),
- (i64 GPR64xsp:$Rn), (i32 GPR32:$Rm), (i64 7)>;
+defm : regoff_pats<"Wm", (add i64:$Rn, (shl (zext i32:$Rm), SHIFT)),
+ (i64 i64:$Rn), (i32 i32:$Rm), (i64 3)>;
-defm : regoff_pats<"Wm", (add GPR64xsp:$Rn, (zext GPR32:$Rm)),
- (i64 GPR64xsp:$Rn), (i32 GPR32:$Rm), (i64 2)>;
+defm : regoff_pats<"Xm", (add i64:$Rn, i64:$Rm),
+ (i64 i64:$Rn), (i64 i64:$Rm), (i64 2)>;
-defm : regoff_pats<"Wm", (add GPR64xsp:$Rn, (shl (zext GPR32:$Rm), SHIFT)),
- (i64 GPR64xsp:$Rn), (i32 GPR32:$Rm), (i64 3)>;
+defm : regoff_pats<"Xm", (add i64:$Rn, (shl i64:$Rm, SHIFT)),
+ (i64 i64:$Rn), (i64 i64:$Rm), (i64 3)>;
-defm : regoff_pats<"Xm", (add GPR64xsp:$Rn, GPR64:$Rm),
- (i64 GPR64xsp:$Rn), (i64 GPR64:$Rm), (i64 2)>;
+//===----------------------------------------------------------------------===//
+// Advanced SIMD (NEON) Support
+//
-defm : regoff_pats<"Xm", (add GPR64xsp:$Rn, (shl GPR64:$Rm, SHIFT)),
- (i64 GPR64xsp:$Rn), (i64 GPR64:$Rm), (i64 3)>;
+include "AArch64InstrNEON.td"
projects / oota-llvm.git / blobdiff