MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_1, 0, TRI);
AddDefaultPred(MIB.addMemOperand(MMO));
} else {
- AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ))
- .addReg(SrcReg, getKillRegState(isKill))
- .addFrameIndex(FI)
- .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
- .addMemOperand(MMO));
+ MachineInstrBuilder MIB =
+ AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
+ .addFrameIndex(FI)
+ .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
+ .addMemOperand(MMO);
+ MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_0, getKillRegState(isKill), TRI);
+ AddDReg(MIB, SrcReg, ARM::DSUBREG_1, 0, TRI);
}
} else {
assert((RC == ARM::QQPRRegisterClass ||
RC == ARM::QQPR_VFP2RegisterClass ||
RC == ARM::QQPR_8RegisterClass) && "Unknown regclass!");
- llvm_unreachable("Not yet implemented!");
+ if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
+ MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VST2q32))
+ .addFrameIndex(FI).addImm(128);
+ MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_0, getKillRegState(isKill), TRI);
+ MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_1, 0, TRI);
+ MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_2, 0, TRI);
+ MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_3, 0, TRI);
+ AddDefaultPred(MIB.addMemOperand(MMO));
+ } else {
+ MachineInstrBuilder MIB =
+ AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
+ .addFrameIndex(FI)
+ .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
+ .addMemOperand(MMO);
+ MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_0, getKillRegState(isKill), TRI);
+ MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_1, 0, TRI);
+ MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_2, 0, TRI);
+ AddDReg(MIB, SrcReg, ARM::DSUBREG_3, 0, TRI);
+ }
}
}
MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_1, RegState::Define, TRI);
AddDefaultPred(MIB.addFrameIndex(FI).addImm(128).addMemOperand(MMO));
} else {
- AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg)
- .addFrameIndex(FI)
- .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
- .addMemOperand(MMO));
+ MachineInstrBuilder MIB =
+ AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
+ .addFrameIndex(FI)
+ .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
+ .addMemOperand(MMO);
+ MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_0, RegState::Define, TRI);
+ AddDReg(MIB, DestReg, ARM::DSUBREG_1, RegState::Define, TRI);
}
} else {
assert((RC == ARM::QQPRRegisterClass ||
RC == ARM::QQPR_VFP2RegisterClass ||
RC == ARM::QQPR_8RegisterClass) && "Unknown regclass!");
- llvm_unreachable("Not yet implemented!");
+ if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
+ MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLD2q32));
+ MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_0, RegState::Define, TRI);
+ MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_1, RegState::Define, TRI);
+ MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_2, RegState::Define, TRI);
+ MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_3, RegState::Define, TRI);
+ AddDefaultPred(MIB.addFrameIndex(FI).addImm(128).addMemOperand(MMO));
+ } else {
+ MachineInstrBuilder MIB =
+ AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
+ .addFrameIndex(FI)
+ .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
+ .addMemOperand(MMO);
+ MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_0, RegState::Define, TRI);
+ MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_1, RegState::Define, TRI);
+ MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_2, RegState::Define, TRI);
+ AddDReg(MIB, DestReg, ARM::DSUBREG_3, RegState::Define, TRI);
+ }
}
}