Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos.

[oota-llvm.git] / lib / Target / ARM / ARMELFWriterInfo.cpp

diff --git a/lib/Target/ARM/ARMELFWriterInfo.cpp b/lib/Target/ARM/ARMELFWriterInfo.cpp
index 85b690fd7aa87de5e2c399eb33e751dac9dd6c27..51e68b4553ff9a7019976523faf4c021569c5473 100644 (file)
--- a/lib/Target/ARM/ARMELFWriterInfo.cpp
+++ b/lib/Target/ARM/ARMELFWriterInfo.cpp
@@ -17,6 +17,7 @@
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetMachine.h"
+#include "llvm/Support/ELF.h"
 
 using namespace llvm;
 
@@ -27,13 +28,27 @@ using namespace llvm;
 ARMELFWriterInfo::ARMELFWriterInfo(TargetMachine &TM)
   : TargetELFWriterInfo(TM.getTargetData()->getPointerSizeInBits() == 64,
                         TM.getTargetData()->isLittleEndian()) {
-  // silently OK construction
 }
 
 ARMELFWriterInfo::~ARMELFWriterInfo() {}
 
 unsigned ARMELFWriterInfo::getRelocationType(unsigned MachineRelTy) const {
-  assert(0 && "ARMELFWriterInfo::getRelocationType() not implemented");
+  switch (MachineRelTy) {
+  case ARM::reloc_arm_absolute:
+  case ARM::reloc_arm_relative:
+  case ARM::reloc_arm_cp_entry:
+  case ARM::reloc_arm_vfp_cp_entry:
+  case ARM::reloc_arm_machine_cp_entry:
+  case ARM::reloc_arm_jt_base:
+  case ARM::reloc_arm_pic_jt:
+    assert(0 && "unsupported ARM relocation type"); break;
+    
+  case ARM::reloc_arm_branch: return ELF::R_ARM_CALL; break;
+  case ARM::reloc_arm_movt:   return ELF::R_ARM_MOVT_ABS; break;
+  case ARM::reloc_arm_movw:   return ELF::R_ARM_MOVW_ABS_NC; break;
+  default:
+    llvm_unreachable("unknown ARM relocation type"); break;
+  }
   return 0;
 }