PTX: Various stylistic and code readability changes recommended by Jim Grosbach.

[oota-llvm.git] / lib / Target / ARM / ARMExpandPseudoInsts.cpp

diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index 0f92d66adeec38be971b6eb20f887a4066066eaf..7872cb90f4e7a75485ab88fe37b77f3ae6f3bd19 100644 (file)
--- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -869,7 +869,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
     case ARM::RRX: {
       // This encodes as "MOVs Rd, Rm, rrx
       MachineInstrBuilder MIB =
-        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
+        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),TII->get(ARM::MOVsi),
                                MI.getOperand(0).getReg())
                        .addOperand(MI.getOperand(1))
                        .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)))
@@ -970,80 +970,6 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
       ExpandMOV32BitImm(MBB, MBBI);
       return true;
 
-    case ARM::VMOVQQ: {
-      unsigned DstReg = MI.getOperand(0).getReg();
-      bool DstIsDead = MI.getOperand(0).isDead();
-      unsigned EvenDst = TRI->getSubReg(DstReg, ARM::qsub_0);
-      unsigned OddDst  = TRI->getSubReg(DstReg, ARM::qsub_1);
-      unsigned SrcReg = MI.getOperand(1).getReg();
-      bool SrcIsKill = MI.getOperand(1).isKill();
-      unsigned EvenSrc = TRI->getSubReg(SrcReg, ARM::qsub_0);
-      unsigned OddSrc  = TRI->getSubReg(SrcReg, ARM::qsub_1);
-      MachineInstrBuilder Even =
-        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
-                               TII->get(ARM::VORRq))
-                       .addReg(EvenDst,
-                               RegState::Define | getDeadRegState(DstIsDead))
-                       .addReg(EvenSrc, getKillRegState(SrcIsKill))
-                       .addReg(EvenSrc, getKillRegState(SrcIsKill)));
-      MachineInstrBuilder Odd =
-        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
-                               TII->get(ARM::VORRq))
-                       .addReg(OddDst,
-                               RegState::Define | getDeadRegState(DstIsDead))
-                       .addReg(OddSrc, getKillRegState(SrcIsKill))
-                       .addReg(OddSrc, getKillRegState(SrcIsKill)));
-      TransferImpOps(MI, Even, Odd);
-      MI.eraseFromParent();
-      return true;
-    }
-
-    case ARM::VMOVQQQQ: {
-      unsigned DstReg = MI.getOperand(0).getReg();
-      bool DstIsDead = MI.getOperand(0).isDead();
-      unsigned Dst0 = TRI->getSubReg(DstReg, ARM::qsub_0);
-      unsigned Dst1 = TRI->getSubReg(DstReg, ARM::qsub_1);
-      unsigned Dst2 = TRI->getSubReg(DstReg, ARM::qsub_2);
-      unsigned Dst3 = TRI->getSubReg(DstReg, ARM::qsub_3);
-      unsigned SrcReg = MI.getOperand(1).getReg();
-      bool SrcIsKill = MI.getOperand(1).isKill();
-      unsigned Src0 = TRI->getSubReg(SrcReg, ARM::qsub_0);
-      unsigned Src1 = TRI->getSubReg(SrcReg, ARM::qsub_1);
-      unsigned Src2 = TRI->getSubReg(SrcReg, ARM::qsub_2);
-      unsigned Src3 = TRI->getSubReg(SrcReg, ARM::qsub_3);
-      MachineInstrBuilder Mov0 =
-        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
-                               TII->get(ARM::VORRq))
-                       .addReg(Dst0,
-                               RegState::Define | getDeadRegState(DstIsDead))
-                       .addReg(Src0, getKillRegState(SrcIsKill))
-                       .addReg(Src0, getKillRegState(SrcIsKill)));
-      MachineInstrBuilder Mov1 =
-        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
-                               TII->get(ARM::VORRq))
-                       .addReg(Dst1,
-                               RegState::Define | getDeadRegState(DstIsDead))
-                       .addReg(Src1, getKillRegState(SrcIsKill))
-                       .addReg(Src1, getKillRegState(SrcIsKill)));
-      MachineInstrBuilder Mov2 =
-        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
-                               TII->get(ARM::VORRq))
-                       .addReg(Dst2,
-                               RegState::Define | getDeadRegState(DstIsDead))
-                       .addReg(Src2, getKillRegState(SrcIsKill))
-                       .addReg(Src2, getKillRegState(SrcIsKill)));
-      MachineInstrBuilder Mov3 =
-        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
-                               TII->get(ARM::VORRq))
-                       .addReg(Dst3,
-                               RegState::Define | getDeadRegState(DstIsDead))
-                       .addReg(Src3, getKillRegState(SrcIsKill))
-                       .addReg(Src3, getKillRegState(SrcIsKill)));
-      TransferImpOps(MI, Mov0, Mov3);
-      MI.eraseFromParent();
-      return true;
-    }
-
     case ARM::VLDMQIA: {
       unsigned NewOpc = ARM::VLDMDIA;
       MachineInstrBuilder MIB =