#include "ARM.h"
#include "ARMBaseInstrInfo.h"
+#include "ARMCallingConv.h"
#include "ARMRegisterInfo.h"
#include "ARMTargetMachine.h"
#include "ARMSubtarget.h"
#include "llvm/GlobalVariable.h"
#include "llvm/Instructions.h"
#include "llvm/IntrinsicInst.h"
+#include "llvm/Module.h"
#include "llvm/CodeGen/Analysis.h"
#include "llvm/CodeGen/FastISel.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "ARMGenFastISel.inc"
// Instruction selection routines.
+ private:
virtual bool ARMSelectLoad(const Instruction *I);
virtual bool ARMSelectStore(const Instruction *I);
virtual bool ARMSelectBranch(const Instruction *I);
virtual bool ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
virtual bool ARMSelectSIToFP(const Instruction *I);
virtual bool ARMSelectFPToSI(const Instruction *I);
+ virtual bool ARMSelectSDiv(const Instruction *I);
// Utility routines.
private:
bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset);
unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
unsigned ARMMaterializeInt(const Constant *C);
+ unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
+ unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
+
+ // Call handling routines.
+ private:
+ CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
+ bool ARMEmitLibcall(const Instruction *I, Function *F);
+ // OptionalDef handling routines.
+ private:
bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
};
} // end anonymous namespace
-// #include "ARMGenCallingConv.inc"
+#include "ARMGenCallingConv.inc"
// DefinesOptionalPredicate - This is different from DefinesPredicate in that
// we don't care about implicit defs here, just places we'll need to add a
return ResultReg;
}
+// TODO: Don't worry about 64-bit now, but when this is fixed remove the
+// checks from the various callers.
+unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
+ if (VT.getSimpleVT().SimpleTy == MVT::f64) return 0;
+
+ unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
+ AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
+ TII.get(ARM::VMOVRS), MoveReg)
+ .addReg(SrcReg));
+ return MoveReg;
+}
+
+unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
+ if (VT.getSimpleVT().SimpleTy == MVT::i64) return 0;
+
+ unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
+ AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
+ TII.get(ARM::VMOVSR), MoveReg)
+ .addReg(SrcReg));
+ return MoveReg;
+}
+
// For double width floating point we need to materialize two constants
// (the high and the low) into integer registers then use a move to get
// the combined constant into an FP reg.
.addFPImm(CFP));
return DestReg;
}
-
- // No 64-bit at the moment.
- if (is64bit) return 0;
-
- // Load this from the constant pool.
- unsigned DestReg = ARMMaterializeInt(cast<Constant>(CFP));
-
- // If we have a floating point constant we expect it in a floating point
- // register.
- unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
- AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
- TII.get(ARM::VMOVRS), MoveReg)
- .addReg(DestReg));
- return MoveReg;
+
+ // Require VFP2 for loading fp constants.
+ if (!Subtarget->hasVFP2()) return false;
+
+ // MachineConstantPool wants an explicit alignment.
+ unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
+ if (Align == 0) {
+ // TODO: Figure out if this is correct.
+ Align = TD.getTypeAllocSize(CFP->getType());
+ }
+ unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
+ unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
+ unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
+
+ // The extra reg is for addrmode5.
+ AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc))
+ .addReg(DestReg).addConstantPoolIndex(Idx)
+ .addReg(0));
+ return DestReg;
}
+// TODO: Verify 64-bit.
unsigned ARMFastISel::ARMMaterializeInt(const Constant *C) {
// MachineConstantPool wants an explicit alignment.
unsigned Align = TD.getPrefTypeAlignment(C->getType());
Align = TD.getTypeAllocSize(C->getType());
}
unsigned Idx = MCP.getConstantPoolIndex(C, Align);
-
unsigned DestReg = createResultReg(TLI.getRegClassFor(MVT::i32));
+
if (isThumb)
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(ARM::t2LDRpci))
.addReg(DestReg).addConstantPoolIndex(Idx));
else
+ // The extra reg and immediate are for addrmode2.
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(ARM::LDRcp))
.addReg(DestReg).addConstantPoolIndex(Idx)
// virtual registers.
if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
return false;
-
Opcode = I->getOpcode();
U = I;
} else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
switch (Opcode) {
default:
- //errs() << "Failing Opcode is: " << *Op1 << "\n";
break;
case Instruction::Alloca: {
assert(false && "Alloca should have been handled earlier!");
}
}
+ // FIXME: Handle global variables.
if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
- //errs() << "Failing GV is: " << GV << "\n";
(void)GV;
return false;
}
static_cast<const ARMBaseInstrInfo&>(TII));
}
}
-
return true;
}
assert(VT.isSimple() && "Non-simple types are invalid here!");
unsigned Opc;
-
+ bool isFloat = false;
switch (VT.getSimpleVT().SimpleTy) {
default:
assert(false && "Trying to emit for an unhandled type!");
case MVT::i32:
Opc = isThumb ? ARM::tLDR : ARM::LDR;
break;
+ case MVT::f32:
+ Opc = ARM::VLDRS;
+ isFloat = true;
+ break;
+ case MVT::f64:
+ Opc = ARM::VLDRD;
+ isFloat = true;
+ break;
}
ResultReg = createResultReg(TLI.getRegClassFor(VT));
// TODO: Fix the Addressing modes so that these can share some code.
// Since this is a Thumb1 load this will work in Thumb1 or 2 mode.
- if (isThumb)
+ // The thumb addressing mode has operands swapped from the arm addressing
+ // mode, the floating point one only has two operands.
+ if (isFloat)
+ AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
+ TII.get(Opc), ResultReg)
+ .addReg(Reg).addImm(Offset));
+ else if (isThumb)
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(Opc), ResultReg)
.addReg(Reg).addImm(Offset).addReg(0));
return true;
}
+bool ARMFastISel::ARMSelectLoad(const Instruction *I) {
+ // Verify we have a legal type before going any further.
+ EVT VT;
+ if (!isLoadTypeLegal(I->getType(), VT))
+ return false;
+
+ // If we're an alloca we know we have a frame index and can emit the load
+ // directly in short order.
+ if (ARMLoadAlloca(I, VT))
+ return true;
+
+ // Our register and offset with innocuous defaults.
+ unsigned Reg = 0;
+ int Offset = 0;
+
+ // See if we can handle this as Reg + Offset
+ if (!ARMComputeRegOffset(I->getOperand(0), Reg, Offset))
+ return false;
+
+ unsigned ResultReg;
+ if (!ARMEmitLoad(VT, ResultReg, Reg, Offset /* 0 */)) return false;
+
+ UpdateValueMap(I, ResultReg);
+ return true;
+}
+
bool ARMFastISel::ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT){
Value *Op1 = I->getOperand(1);
bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
unsigned DstReg, int Offset) {
unsigned StrOpc;
+ bool isFloat = false;
switch (VT.getSimpleVT().SimpleTy) {
default: return false;
case MVT::i1:
case MVT::f32:
if (!Subtarget->hasVFP2()) return false;
StrOpc = ARM::VSTRS;
+ isFloat = true;
break;
case MVT::f64:
if (!Subtarget->hasVFP2()) return false;
StrOpc = ARM::VSTRD;
+ isFloat = true;
break;
}
- if (isThumb)
+ // The thumb addressing mode has operands swapped from the arm addressing
+ // mode, the floating point one only has two operands.
+ if (isFloat)
+ AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
+ TII.get(StrOpc), SrcReg)
+ .addReg(DstReg).addImm(Offset));
+ else if (isThumb)
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(StrOpc), SrcReg)
.addReg(DstReg).addImm(Offset).addReg(0));
+
else
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(StrOpc), SrcReg)
if (!ARMEmitStore(VT, SrcReg, Reg, Offset /* 0 */)) return false;
- return false;
+ return true;
}
-bool ARMFastISel::ARMSelectLoad(const Instruction *I) {
- // Verify we have a legal type before going any further.
- EVT VT;
- if (!isLoadTypeLegal(I->getType(), VT))
- return false;
-
- // If we're an alloca we know we have a frame index and can emit the load
- // directly in short order.
- if (ARMLoadAlloca(I, VT))
- return true;
-
- // Our register and offset with innocuous defaults.
- unsigned Reg = 0;
- int Offset = 0;
-
- // See if we can handle this as Reg + Offset
- if (!ARMComputeRegOffset(I->getOperand(0), Reg, Offset))
- return false;
-
- unsigned ResultReg;
- if (!ARMEmitLoad(VT, ResultReg, Reg, Offset /* 0 */)) return false;
-
- UpdateValueMap(I, ResultReg);
- return true;
+static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
+ switch (Pred) {
+ // Needs two compares...
+ case CmpInst::FCMP_ONE:
+ case CmpInst::FCMP_UEQ:
+ default:
+ assert(false && "Unhandled CmpInst::Predicate!");
+ return ARMCC::AL;
+ case CmpInst::ICMP_EQ:
+ case CmpInst::FCMP_OEQ:
+ return ARMCC::EQ;
+ case CmpInst::ICMP_SGT:
+ case CmpInst::FCMP_OGT:
+ return ARMCC::GT;
+ case CmpInst::ICMP_SGE:
+ case CmpInst::FCMP_OGE:
+ return ARMCC::GE;
+ case CmpInst::ICMP_UGT:
+ case CmpInst::FCMP_UGT:
+ return ARMCC::HI;
+ case CmpInst::FCMP_OLT:
+ return ARMCC::MI;
+ case CmpInst::ICMP_ULE:
+ case CmpInst::FCMP_OLE:
+ return ARMCC::LS;
+ case CmpInst::FCMP_ORD:
+ return ARMCC::VC;
+ case CmpInst::FCMP_UNO:
+ return ARMCC::VS;
+ case CmpInst::FCMP_UGE:
+ return ARMCC::PL;
+ case CmpInst::ICMP_SLT:
+ case CmpInst::FCMP_ULT:
+ return ARMCC::LT;
+ case CmpInst::ICMP_SLE:
+ case CmpInst::FCMP_ULE:
+ return ARMCC::LE;
+ case CmpInst::FCMP_UNE:
+ case CmpInst::ICMP_NE:
+ return ARMCC::NE;
+ case CmpInst::ICMP_UGE:
+ return ARMCC::HS;
+ case CmpInst::ICMP_ULT:
+ return ARMCC::LO;
+ }
}
bool ARMFastISel::ARMSelectBranch(const Instruction *I) {
MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
// Simple branch support.
- unsigned CondReg = getRegForValue(BI->getCondition());
+ // TODO: Hopefully we've already handled the condition since we won't
+ // have left an update in the value map. See the TODO below in ARMSelectCMP.
+ Value *Cond = BI->getCondition();
+ unsigned CondReg = getRegForValue(Cond);
if (CondReg == 0) return false;
- unsigned CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
+ ARMCC::CondCodes ARMPred = ARMCC::NE;
+ CmpInst *CI = dyn_cast<CmpInst>(Cond);
+ if (!CI) return false;
+
+ // Get the compare predicate.
+ ARMPred = getComparePred(CI->getPredicate());
+
+ // We may not handle every CC for now.
+ if (ARMPred == ARMCC::AL) return false;
+
unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
- AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
- .addReg(CondReg).addReg(CondReg));
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
- .addMBB(TBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
+ .addMBB(TBB).addImm(ARMPred).addReg(CondReg);
FastEmitBranch(FBB, DL);
FuncInfo.MBB->addSuccessor(TBB);
- return true;
+ return true;
}
bool ARMFastISel::ARMSelectCmp(const Instruction *I) {
return false;
unsigned CmpOpc;
+ unsigned DestReg;
switch (VT.getSimpleVT().SimpleTy) {
default: return false;
// TODO: Verify compares.
case MVT::f32:
CmpOpc = ARM::VCMPES;
+ DestReg = ARM::FPSCR;
break;
case MVT::f64:
CmpOpc = ARM::VCMPED;
+ DestReg = ARM::FPSCR;
break;
case MVT::i32:
CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
+ DestReg = ARM::CPSR;
break;
}
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
.addReg(Arg1).addReg(Arg2));
- // For floating point we need to move the result to a register we can
- // actually do something with.
+ // For floating point we need to move the result to a comparison register
+ // that we can then use for branches.
if (isFloat)
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(ARM::FMSTAT)));
- // TODO: How to update the value map when there's no result reg?
+ // Update the value to the implicit def reg.
+ UpdateValueMap(I, DestReg);
return true;
}
if (Op == 0) return false;
unsigned Result = createResultReg(ARM::DPRRegisterClass);
-
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(ARM::VCVTDS), Result)
.addReg(Op));
if (Op == 0) return false;
unsigned Result = createResultReg(ARM::SPRRegisterClass);
-
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(ARM::VCVTSD), Result)
.addReg(Op));
// Make sure we have VFP.
if (!Subtarget->hasVFP2()) return false;
- EVT VT;
+ EVT DstVT;
const Type *Ty = I->getType();
- if (!isTypeLegal(Ty, VT))
+ if (!isTypeLegal(Ty, DstVT))
return false;
unsigned Op = getRegForValue(I->getOperand(0));
if (Op == 0) return false;
+ // The conversion routine works on fp-reg to fp-reg and the operand above
+ // was an integer, move it to the fp registers if possible.
+ unsigned FP = ARMMoveToFPReg(DstVT, Op);
+ if (FP == 0) return false;
+
unsigned Opc;
if (Ty->isFloatTy()) Opc = ARM::VSITOS;
else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
else return 0;
- unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
+ unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
ResultReg)
- .addReg(Op));
+ .addReg(FP));
UpdateValueMap(I, ResultReg);
return true;
}
// Make sure we have VFP.
if (!Subtarget->hasVFP2()) return false;
- EVT VT;
+ EVT DstVT;
const Type *RetTy = I->getType();
- if (!isTypeLegal(RetTy, VT))
+ if (!isTypeLegal(RetTy, DstVT))
return false;
unsigned Op = getRegForValue(I->getOperand(0));
if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
else return 0;
+ EVT OpVT = TLI.getValueType(OpTy, true);
- unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
+ unsigned ResultReg = createResultReg(TLI.getRegClassFor(OpVT));
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
ResultReg)
.addReg(Op));
- UpdateValueMap(I, ResultReg);
+
+ // This result needs to be in an integer register, but the conversion only
+ // takes place in fp-regs.
+ unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
+ if (IntReg == 0) return false;
+
+ UpdateValueMap(I, IntReg);
return true;
}
return true;
}
+// Call Handling Code
+
+// This is largely taken directly from CCAssignFnForNode - we don't support
+// varargs in FastISel so that part has been removed.
+// TODO: We may not support all of this.
+CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) {
+ switch (CC) {
+ default:
+ llvm_unreachable("Unsupported calling convention");
+ case CallingConv::C:
+ case CallingConv::Fast:
+ // Use target triple & subtarget features to do actual dispatch.
+ if (Subtarget->isAAPCS_ABI()) {
+ if (Subtarget->hasVFP2() &&
+ FloatABIType == FloatABI::Hard)
+ return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
+ else
+ return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
+ } else
+ return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
+ case CallingConv::ARM_AAPCS_VFP:
+ return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
+ case CallingConv::ARM_AAPCS:
+ return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
+ case CallingConv::ARM_APCS:
+ return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
+ }
+}
+
+// A quick function that will emit a call for a named libcall in F with the
+// vector of passed arguments for the Instruction in I. We can assume that we
+// can emit a call for any libcall we can produce. This is an abridged version
+// of the full call infrastructure since we won't need to worry about things
+// like computed function pointers or strange arguments at call sites.
+// TODO: Try to unify this and the normal call bits for ARM, then try to unify
+// with X86.
+bool ARMFastISel::ARMEmitLibcall(const Instruction *I, Function *F) {
+ CallingConv::ID CC = F->getCallingConv();
+
+ // Handle *simple* calls for now.
+ const Type *RetTy = F->getReturnType();
+ EVT RetVT;
+ if (RetTy->isVoidTy())
+ RetVT = MVT::isVoid;
+ else if (!isTypeLegal(RetTy, RetVT))
+ return false;
+
+ assert(!F->isVarArg() && "Vararg libcall?!");
+
+ // Abridged from the X86 FastISel call selection mechanism
+ SmallVector<Value*, 8> Args;
+ SmallVector<unsigned, 8> ArgRegs;
+ SmallVector<EVT, 8> ArgVTs;
+ SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
+ Args.reserve(I->getNumOperands());
+ ArgRegs.reserve(I->getNumOperands());
+ ArgVTs.reserve(I->getNumOperands());
+ ArgFlags.reserve(I->getNumOperands());
+ for (unsigned i = 0; i < Args.size(); ++i) {
+ Value *Op = I->getOperand(i);
+ unsigned Arg = getRegForValue(Op);
+ if (Arg == 0) return false;
+
+ const Type *ArgTy = Op->getType();
+ EVT ArgVT;
+ if (!isTypeLegal(ArgTy, ArgVT)) return false;
+
+ ISD::ArgFlagsTy Flags;
+ unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
+ Flags.setOrigAlign(OriginalAlignment);
+
+ Args.push_back(Op);
+ ArgRegs.push_back(Arg);
+ ArgVTs.push_back(ArgVT);
+ ArgFlags.push_back(Flags);
+ }
+
+ SmallVector<CCValAssign, 16> ArgLocs;
+ CCState CCInfo(CC, false, TM, ArgLocs, F->getContext());
+ CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
+
+ // Process the args.
+ SmallVector<unsigned, 4> RegArgs;
+ for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
+ CCValAssign &VA = ArgLocs[i];
+ unsigned Arg = ArgRegs[VA.getValNo()];
+ EVT ArgVT = ArgVTs[VA.getValNo()];
+
+ // Should we ever have to promote?
+ switch (VA.getLocInfo()) {
+ case CCValAssign::Full: break;
+ default:
+ assert(false && "Handle arg promotion for libcalls?");
+ return false;
+ }
+
+ // Now copy/store arg to correct locations.
+ if (VA.isRegLoc()) {
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
+ VA.getLocReg()).addReg(Arg);
+ RegArgs.push_back(VA.getLocReg());
+ } else {
+ // Need to store
+ return false;
+ }
+ }
+
+ // Issue the call, BLr9 for darwin, BL otherwise.
+ MachineInstrBuilder MIB;
+ unsigned CallOpc;
+ if(isThumb)
+ CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLr9 : ARM::tBL;
+ else
+ CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
+ MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
+ .addGlobalAddress(F, 0, 0);
+
+ // Add implicit physical register uses to the call.
+ for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
+ MIB.addReg(RegArgs[i]);
+
+ // Now the return value.
+ SmallVector<unsigned, 4> UsedRegs;
+ if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) {
+ SmallVector<CCValAssign, 16> RVLocs;
+ CCState CCInfo(CC, false, TM, RVLocs, F->getContext());
+ CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
+
+ // Copy all of the result registers out of their specified physreg.
+ assert(RVLocs.size() == 1 && "Can't handle multi-value calls!");
+ EVT CopyVT = RVLocs[0].getValVT();
+ TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
+
+ unsigned ResultReg = createResultReg(DstRC);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
+ ResultReg).addReg(RVLocs[0].getLocReg());
+ UsedRegs.push_back(RVLocs[0].getLocReg());
+
+ // Finally update the result.
+ UpdateValueMap(I, ResultReg);
+ }
+
+ // Set all unused physreg defs as dead.
+ static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
+
+ return true;
+}
+
+bool ARMFastISel::ARMSelectSDiv(const Instruction *I) {
+ EVT VT;
+ const Type *Ty = I->getType();
+ if (!isTypeLegal(Ty, VT))
+ return false;
+
+ // If we have integer div support we should have gotten already, emit a
+ // libcall.
+ RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
+ if (VT == MVT::i16)
+ LC = RTLIB::SDIV_I16;
+ else if (VT == MVT::i32)
+ LC = RTLIB::SDIV_I32;
+ else if (VT == MVT::i64)
+ LC = RTLIB::SDIV_I64;
+ else if (VT == MVT::i128)
+ LC = RTLIB::SDIV_I128;
+ assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
+
+ // Binary operand with all the same type.
+ std::vector<const Type*> ArgTys;
+ ArgTys.push_back(Ty);
+ ArgTys.push_back(Ty);
+ const FunctionType *FTy = FunctionType::get(Ty, ArgTys, false);
+ Function *F = Function::Create(FTy, GlobalValue::ExternalLinkage,
+ TLI.getLibcallName(LC));
+ if (Subtarget->isAAPCS_ABI())
+ F->setCallingConv(CallingConv::ARM_AAPCS);
+ else
+ F->setCallingConv(I->getParent()->getParent()->getCallingConv());
+
+ return ARMEmitLibcall(I, F);
+}
+
// TODO: SoftFP support.
bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
// No Thumb-1 for now.
return ARMSelectBinaryOp(I, ISD::FSUB);
case Instruction::FMul:
return ARMSelectBinaryOp(I, ISD::FMUL);
+ case Instruction::SDiv:
+ return ARMSelectSDiv(I);
default: break;
}
return false;
projects / oota-llvm.git / blobdiff