// Don't match base register only case. That is matched to a separate
// lower complexity pattern with explicit register operand.
if (ShOpcVal == ARM_AM::no_shift) return false;
-
+
BaseReg = N.getOperand(0);
unsigned ShImmVal = 0;
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
MVT::i32);
return true;
}
-
+
// Match simple R +/- imm12 operands.
if (N.getOpcode() == ISD::ADD)
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
return true;
}
}
-
+
// Otherwise this is R +/- [possibly shifted] R
ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
unsigned ShAmt = 0;
-
+
Base = N.getOperand(0);
Offset = N.getOperand(1);
-
+
if (ShOpcVal != ARM_AM::no_shift) {
// Check to see if the RHS of the shift is a constant, if not, we can't fold
// it.
ShOpcVal = ARM_AM::no_shift;
}
}
-
+
// Try matching (R shl C) + (R).
if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
}
}
}
-
+
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
MVT::i32);
return true;
Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
return true;
}
-
+
if (N.getOpcode() != ISD::ADD) {
Base = N;
if (N.getOpcode() == ISD::FrameIndex) {
Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
return true;
}
-
+
// If the RHS is +/- imm8, fold into addr mode.
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
int RHSC = (int)RHS->getZExtValue();
return true;
}
}
-
+
Base = N.getOperand(0);
Offset = N.getOperand(1);
Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
MVT::i32);
return true;
}
-
+
// If the RHS is +/- imm8, fold into addr mode.
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
int RHSC = (int)RHS->getZExtValue();
}
}
}
-
+
Base = N;
Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
MVT::i32);
}
}
}
-
+
return false;
}
SDValue &Base, SDValue &OffImm) {
// Match simple R + imm12 operands.
- // Match frame index...
- if ((N.getOpcode() != ISD::ADD) && (N.getOpcode() != ISD::SUB)) {
+ // Base only.
+ if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
if (N.getOpcode() == ISD::FrameIndex) {
+ // Match frame index...
int FI = cast<FrameIndexSDNode>(N)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
OffImm = CurDAG->getTargetConstant(0, MVT::i32);
return true;
- }
- return false;
+ } else if (N.getOpcode() == ARMISD::Wrapper) {
+ Base = N.getOperand(0);
+ if (Base.getOpcode() == ISD::TargetConstantPool)
+ return false; // We want to select t2LDRpci instead.
+ } else
+ Base = N;
+ OffImm = CurDAG->getTargetConstant(0, MVT::i32);
+ return true;
}
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
+ if (SelectT2AddrModeImm8(Op, N, Base, OffImm))
+ // Let t2LDRi8 handle (R - imm8).
+ return false;
+
int RHSC = (int)RHS->getZExtValue();
if (N.getOpcode() == ISD::SUB)
RHSC = -RHSC;
}
}
- return false;
+ // Base only.
+ Base = N;
+ OffImm = CurDAG->getTargetConstant(0, MVT::i32);
+ return true;
}
bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue Op, SDValue N,
SDValue &Base, SDValue &OffImm) {
// Match simple R - imm8 operands.
- if ((N.getOpcode() == ISD::ADD) || (N.getOpcode() == ISD::SUB)) {
+ if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
int RHSC = (int)RHS->getSExtValue();
if (N.getOpcode() == ISD::SUB)
RHSC = -RHSC;
-
- if ((RHSC >= -255) && (RHSC <= 0)) { // 8 bits (always negative)
- Base = N.getOperand(0);
+
+ if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
+ Base = N.getOperand(0);
if (Base.getOpcode() == ISD::FrameIndex) {
int FI = cast<FrameIndexSDNode>(Base)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N,
SDValue &Base,
SDValue &OffReg, SDValue &ShImm) {
- // Base only.
- if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
- Base = N;
- if (N.getOpcode() == ISD::FrameIndex) {
- return false; // we want to select t2LDRri12 instead
- } else if (N.getOpcode() == ARMISD::Wrapper) {
- Base = N.getOperand(0);
- if (Base.getOpcode() == ISD::TargetConstantPool)
- return false; // We want to select t2LDRpci instead.
- }
- OffReg = CurDAG->getRegister(0, MVT::i32);
- ShImm = CurDAG->getTargetConstant(0, MVT::i32);
- return true;
- }
+ // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
+ if (N.getOpcode() != ISD::ADD)
+ return false;
- // Leave (R +/- imm) for other address modes... unless they can't
- // handle them
- if (dyn_cast<ConstantSDNode>(N.getOperand(1)) != NULL) {
- SDValue OffImm;
- if (SelectT2AddrModeImm12(Op, N, Base, OffImm) ||
- SelectT2AddrModeImm8 (Op, N, Base, OffImm))
+ // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
+ if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
+ int RHSC = (int)RHS->getZExtValue();
+ if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
+ return false;
+ else if (RHSC < 0 && RHSC >= -255) // 8 bits
return false;
}
- // Thumb2 does not support (R - R) or (R - (R << [1,2,3])).
- if (N.getOpcode() == ISD::SUB) {
- Base = N;
- OffReg = CurDAG->getRegister(0, MVT::i32);
- ShImm = CurDAG->getTargetConstant(0, MVT::i32);
- return true;
- }
-
- assert(N.getOpcode() == ISD::ADD);
-
// Look for (R + R) or (R + (R << [1,2,3])).
unsigned ShAmt = 0;
Base = N.getOperand(0);
ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
if (ShOpcVal == ARM_AM::lsl)
std::swap(Base, OffReg);
- }
-
+ }
+
if (ShOpcVal == ARM_AM::lsl) {
// Check to see if the RHS of the shift is a constant, if not, we can't fold
// it.
ShOpcVal = ARM_AM::no_shift;
}
}
-
+
ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
return true;
if (AM == ISD::UNINDEXED)
return NULL;
- MVT LoadedVT = LD->getMemoryVT();
+ EVT LoadedVT = LD->getMemoryVT();
SDValue Offset, AMOpc;
bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
unsigned Opcode = 0;
if (AM == ISD::UNINDEXED)
return NULL;
- MVT LoadedVT = LD->getMemoryVT();
+ EVT LoadedVT = LD->getMemoryVT();
bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
SDValue Offset;
bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
unsigned Opcode = 0;
bool Match = false;
if (SelectT2AddrModeImm8Offset(Op, LD->getOffset(), Offset)) {
- switch (LoadedVT.getSimpleVT()) {
+ switch (LoadedVT.getSimpleVT().SimpleTy) {
case MVT::i32:
Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
break;
SDNode *ARMDAGToDAGISel::SelectDYN_ALLOC(SDValue Op) {
SDNode *N = Op.getNode();
DebugLoc dl = N->getDebugLoc();
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
SDValue Chain = Op.getOperand(0);
SDValue Size = Op.getOperand(1);
SDValue Align = Op.getOperand(2);
Chain);
if (Subtarget->isThumb1Only()) {
- // Use tADDrSPr since Thumb1 does not have a sub r, sp, r. ARMISelLowering
+ // Use tADDspr since Thumb1 does not have a sub r, sp, r. ARMISelLowering
// should have negated the size operand already. FIXME: We can't insert
// new target independent node at this stage so we are forced to negate
- // it earlier. Is there a better solution?
+ // it earlier. Is there a better solution?
return CurDAG->SelectNodeTo(N, ARM::tADDspr_, VT, MVT::Other, SP, Size,
Chain);
} else if (Subtarget->isThumb2()) {
!ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
if (UseCP) {
SDValue CPIdx =
- CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
+ CurDAG->getTargetConstantPool(ConstantInt::get(
+ Type::getInt32Ty(*CurDAG->getContext()), Val),
TLI.getPointerTy());
SDNode *ResNode;
Ops, 4);
} else {
SDValue Ops[] = {
- CPIdx,
+ CPIdx,
CurDAG->getRegister(0, MVT::i32),
CurDAG->getTargetConstant(0, MVT::i32),
getAL(CurDAG),
ReplaceUses(Op, SDValue(ResNode, 0));
return NULL;
}
-
+
// Other cases are autogenerated.
break;
}
- case ISD::ConstantFP: {
- ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(N);
- MVT VT = CFP->getValueType(0);
- ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
- SDValue CPIdx = CurDAG->getTargetConstantPool(LLVMC, TLI.getPointerTy());
- SDNode *ResNode;
- SDValue Ops[] = {
- CPIdx,
- CurDAG->getTargetConstant(0, MVT::i32),
- getAL(CurDAG),
- CurDAG->getRegister(0, MVT::i32),
- CurDAG->getEntryNode()
- };
- unsigned Opc = (VT == MVT::f32) ? ARM::FLDS : ARM::FLDD;
- ResNode=CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Ops, 5);
- ReplaceUses(Op, SDValue(ResNode, 0));
- return NULL;
- }
case ISD::FrameIndex: {
// Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
int FI = cast<FrameIndexSDNode>(N)->getIndex();
// Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
// Pattern complexity = 6 cost = 1 size = 0
- unsigned Opc = Subtarget->isThumb() ?
+ unsigned Opc = Subtarget->isThumb() ?
((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
SDValue Chain = Op.getOperand(0);
SDValue N1 = Op.getOperand(1);
cast<ConstantSDNode>(N2)->getZExtValue()),
MVT::i32);
SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
- SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, MVT::Other,
+ SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, MVT::Other,
MVT::Flag, Ops, 5);
Chain = SDValue(ResNode, 0);
if (Op.getNode()->getNumValues() == 2) {
return NULL;
}
case ARMISD::CMOV: {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
SDValue N0 = Op.getOperand(0);
SDValue N1 = Op.getOperand(1);
SDValue N2 = Op.getOperand(2);
MVT::i32);
SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
unsigned Opc = 0;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: assert(false && "Illegal conditional move type!");
break;
case MVT::i32:
Opc = Subtarget->isThumb()
- ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr)
+ ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
: ARM::MOVCCr;
break;
case MVT::f32:
break;
case MVT::f64:
Opc = ARM::FCPYDcc;
- break;
+ break;
}
return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
}
case ARMISD::CNEG: {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
SDValue N0 = Op.getOperand(0);
SDValue N1 = Op.getOperand(1);
SDValue N2 = Op.getOperand(2);
MVT::i32);
SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
unsigned Opc = 0;
- switch (VT.getSimpleVT()) {
+ switch (VT.getSimpleVT().SimpleTy) {
default: assert(false && "Illegal conditional move type!");
break;
case MVT::f32:
ReplaceUses(Op.getValue(0), Chain);
return NULL;
}
-
+
SDValue Tmp1 = CurDAG->getTargetFrameIndex(FINode->getIndex(),
TLI.getPointerTy());
SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());
}
case ISD::VECTOR_SHUFFLE: {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
// Match 128-bit splat to VDUPLANEQ. (This could be done with a Pat in
// ARMInstrNEON.td but it is awkward because the shuffle mask needs to be
Op.getOperand(1).getOpcode() == ISD::UNDEF) {
unsigned LaneVal = SVOp->getSplatIndex();
- MVT HalfVT;
+ EVT HalfVT;
unsigned Opc = 0;
- switch (VT.getVectorElementType().getSimpleVT()) {
+ switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled VDUP splat type");
case MVT::i8: Opc = ARM::VDUPLN8q; HalfVT = MVT::v8i8; break;
case MVT::i16: Opc = ARM::VDUPLN16q; HalfVT = MVT::v4i16; break;
if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
return NULL;
unsigned Opc = 0;
- MVT VT = Op.getValueType();
- switch (VT.getSimpleVT()) {
+ EVT VT = Op.getValueType();
+ switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled VLD2D type");
case MVT::v8i8: Opc = ARM::VLD2d8; break;
case MVT::v4i16: Opc = ARM::VLD2d16; break;
case MVT::v2f32:
case MVT::v2i32: Opc = ARM::VLD2d32; break;
}
- const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
- return CurDAG->getTargetNode(Opc, dl, VT, VT, MVT::Other, Ops, 3);
+ SDValue Chain = N->getOperand(0);
+ const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
+ return CurDAG->getTargetNode(Opc, dl, VT, VT, MVT::Other, Ops, 4);
}
case ARMISD::VLD3D: {
if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
return NULL;
unsigned Opc = 0;
- MVT VT = Op.getValueType();
- switch (VT.getSimpleVT()) {
+ EVT VT = Op.getValueType();
+ switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled VLD3D type");
case MVT::v8i8: Opc = ARM::VLD3d8; break;
case MVT::v4i16: Opc = ARM::VLD3d16; break;
case MVT::v2f32:
case MVT::v2i32: Opc = ARM::VLD3d32; break;
}
- const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
- return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 3);
+ SDValue Chain = N->getOperand(0);
+ const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
+ return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 4);
}
case ARMISD::VLD4D: {
if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
return NULL;
unsigned Opc = 0;
- MVT VT = Op.getValueType();
- switch (VT.getSimpleVT()) {
+ EVT VT = Op.getValueType();
+ switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled VLD4D type");
case MVT::v8i8: Opc = ARM::VLD4d8; break;
case MVT::v4i16: Opc = ARM::VLD4d16; break;
case MVT::v2f32:
case MVT::v2i32: Opc = ARM::VLD4d32; break;
}
- const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
- std::vector<MVT> ResTys(4, VT);
+ SDValue Chain = N->getOperand(0);
+ const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
+ std::vector<EVT> ResTys(4, VT);
ResTys.push_back(MVT::Other);
- return CurDAG->getTargetNode(Opc, dl, ResTys, Ops, 3);
+ return CurDAG->getTargetNode(Opc, dl, ResTys, Ops, 4);
}
case ARMISD::VST2D: {
if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
return NULL;
unsigned Opc = 0;
- switch (N->getOperand(2).getValueType().getSimpleVT()) {
+ switch (N->getOperand(2).getValueType().getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled VST2D type");
case MVT::v8i8: Opc = ARM::VST2d8; break;
case MVT::v4i16: Opc = ARM::VST2d16; break;
case MVT::v2f32:
case MVT::v2i32: Opc = ARM::VST2d32; break;
}
+ SDValue Chain = N->getOperand(0);
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
- N->getOperand(2), N->getOperand(3) };
- return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 5);
+ N->getOperand(2), N->getOperand(3), Chain };
+ return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 6);
}
case ARMISD::VST3D: {
if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
return NULL;
unsigned Opc = 0;
- switch (N->getOperand(2).getValueType().getSimpleVT()) {
+ switch (N->getOperand(2).getValueType().getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled VST3D type");
case MVT::v8i8: Opc = ARM::VST3d8; break;
case MVT::v4i16: Opc = ARM::VST3d16; break;
case MVT::v2f32:
case MVT::v2i32: Opc = ARM::VST3d32; break;
}
+ SDValue Chain = N->getOperand(0);
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
N->getOperand(2), N->getOperand(3),
- N->getOperand(4) };
- return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 6);
+ N->getOperand(4), Chain };
+ return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7);
}
case ARMISD::VST4D: {
if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
return NULL;
unsigned Opc = 0;
- switch (N->getOperand(2).getValueType().getSimpleVT()) {
+ switch (N->getOperand(2).getValueType().getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled VST4D type");
case MVT::v8i8: Opc = ARM::VST4d8; break;
case MVT::v4i16: Opc = ARM::VST4d16; break;
case MVT::v2f32:
case MVT::v2i32: Opc = ARM::VST4d32; break;
}
+ SDValue Chain = N->getOperand(0);
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
N->getOperand(2), N->getOperand(3),
- N->getOperand(4), N->getOperand(5) };
- return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7);
+ N->getOperand(4), N->getOperand(5), Chain };
+ return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 8);
}
case ISD::INTRINSIC_WO_CHAIN: {
unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
unsigned Opc = 0;
// Match intrinsics that return multiple values.
switch (IntNo) {
default: break;
- case Intrinsic::arm_neon_vtrni:
- case Intrinsic::arm_neon_vtrnf:
- switch (VT.getSimpleVT()) {
+ case Intrinsic::arm_neon_vtrn:
+ switch (VT.getSimpleVT().SimpleTy) {
default: return NULL;
case MVT::v8i8: Opc = ARM::VTRNd8; break;
case MVT::v4i16: Opc = ARM::VTRNd16; break;
return CurDAG->getTargetNode(Opc, dl, VT, VT, N->getOperand(1),
N->getOperand(2));
- case Intrinsic::arm_neon_vuzpi:
- case Intrinsic::arm_neon_vuzpf:
- switch (VT.getSimpleVT()) {
+ case Intrinsic::arm_neon_vuzp:
+ switch (VT.getSimpleVT().SimpleTy) {
default: return NULL;
case MVT::v8i8: Opc = ARM::VUZPd8; break;
case MVT::v4i16: Opc = ARM::VUZPd16; break;
return CurDAG->getTargetNode(Opc, dl, VT, VT, N->getOperand(1),
N->getOperand(2));
- case Intrinsic::arm_neon_vzipi:
- case Intrinsic::arm_neon_vzipf:
- switch (VT.getSimpleVT()) {
+ case Intrinsic::arm_neon_vzip:
+ switch (VT.getSimpleVT().SimpleTy) {
default: return NULL;
case MVT::v8i8: Opc = ARM::VZIPd8; break;
case MVT::v4i16: Opc = ARM::VZIPd16; break;
SDValue Base, Offset, Opc;
if (!SelectAddrMode2(Op, Op, Base, Offset, Opc))
return true;
-
+
OutOps.push_back(Base);
OutOps.push_back(Offset);
OutOps.push_back(Opc);
projects / oota-llvm.git / blobdiff