Updated VS build system. Patch provided by Cedric Venet:

[oota-llvm.git] / lib / Target / ARM / ARMISelDAGToDAG.cpp

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 933651d8b15cc1035a88cbf75b15a99d917ea90c..eaa16fc9d68dd8fb440d4d504df7238afeb386a0 100644 (file)
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -2,8 +2,8 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by Chris Lattner and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
@@ -25,9 +25,9 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
-#include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/Target/TargetLowering.h"
 #include "llvm/Target/TargetOptions.h"
+#include "llvm/Support/Compiler.h"
 #include "llvm/Support/Debug.h"
 using namespace llvm;
 
@@ -641,7 +641,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
     return CurDAG->getTargetNode(ARM::FMRRD, MVT::i32, MVT::i32,
                                  Op.getOperand(0), getAL(CurDAG),
                                  CurDAG->getRegister(0, MVT::i32));
-  case ARMISD::MULHILOU: {
+  case ISD::UMUL_LOHI: {
     AddToISelQueue(Op.getOperand(0));
     AddToISelQueue(Op.getOperand(1));
     SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1),
@@ -649,7 +649,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
                         CurDAG->getRegister(0, MVT::i32) };
     return CurDAG->getTargetNode(ARM::UMULL, MVT::i32, MVT::i32, Ops, 5);
   }
-  case ARMISD::MULHILOS: {
+  case ISD::SMUL_LOHI: {
     AddToISelQueue(Op.getOperand(0));
     AddToISelQueue(Op.getOperand(1));
     SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1),
@@ -660,7 +660,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
   case ISD::LOAD: {
     LoadSDNode *LD = cast<LoadSDNode>(Op);
     ISD::MemIndexedMode AM = LD->getAddressingMode();
-    MVT::ValueType LoadedVT = LD->getLoadedVT();
+    MVT LoadedVT = LD->getMemoryVT();
     if (AM != ISD::UNINDEXED) {
       SDOperand Offset, AMOpc;
       bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
@@ -732,14 +732,16 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
     SDOperand Ops[] = { N1, Tmp2, N3, Chain, InFlag };
     SDNode *ResNode = CurDAG->getTargetNode(Opc, MVT::Other, MVT::Flag, Ops, 5);
     Chain = SDOperand(ResNode, 0);
-    InFlag = SDOperand(ResNode, 1);
-    ReplaceUses(SDOperand(Op.Val, 1), InFlag);
+    if (Op.Val->getNumValues() == 2) {
+      InFlag = SDOperand(ResNode, 1);
+      ReplaceUses(SDOperand(Op.Val, 1), InFlag);
+    }
     ReplaceUses(SDOperand(Op.Val, 0), SDOperand(Chain.Val, Chain.ResNo));
     return NULL;
   }
   case ARMISD::CMOV: {
     bool isThumb = Subtarget->isThumb();
-    MVT::ValueType VT = Op.getValueType();
+    MVT VT = Op.getValueType();
     SDOperand N0 = Op.getOperand(0);
     SDOperand N1 = Op.getOperand(1);
     SDOperand N2 = Op.getOperand(2);
@@ -803,7 +805,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
                                cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
     SDOperand Ops[] = { N0, N1, Tmp2, N3, InFlag };
     unsigned Opc = 0;
-    switch (VT) {
+    switch (VT.getSimpleVT()) {
     default: assert(false && "Illegal conditional move type!");
       break;
     case MVT::i32:
@@ -819,7 +821,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
     return CurDAG->SelectNodeTo(Op.Val, Opc, VT, Ops, 5);
   }
   case ARMISD::CNEG: {
-    MVT::ValueType VT = Op.getValueType();
+    MVT VT = Op.getValueType();
     SDOperand N0 = Op.getOperand(0);
     SDOperand N1 = Op.getOperand(1);
     SDOperand N2 = Op.getOperand(2);
@@ -835,7 +837,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
                                cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
     SDOperand Ops[] = { N0, N1, Tmp2, N3, InFlag };
     unsigned Opc = 0;
-    switch (VT) {
+    switch (VT.getSimpleVT()) {
     default: assert(false && "Illegal conditional move type!");
       break;
     case MVT::f32: