-//===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
+//===- ARMInstrFormats.td - ARM Instruction Formats ----------*- tablegen -*-=//
//
// The LLVM Compiler Infrastructure
//
// Misc flags.
-// the instruction has a Rn register operand.
+// The instruction has an Rn register operand.
// UnaryDP - Indicates this is a unary data processing instruction, i.e.
// it doesn't have a Rn operand.
class UnaryDP { bit isUnaryDataProc = 1; }
def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
//===----------------------------------------------------------------------===//
-
// ARM special operands.
//
let SuperClasses = [];
}
+def CCOutOperand : AsmOperandClass {
+ let Name = "CCOut";
+ let SuperClasses = [];
+}
+
// ARM Predicate operand. Default to 14 = always (AL). Second part is CC
// register whose default is 0 (no register).
def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
let EncoderMethod = "getCCOutOpValue";
let PrintMethod = "printSBitModifierOperand";
+ let ParserMatchClass = CCOutOperand;
}
// Same as cc_out except it defaults to setting CPSR.
def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
let EncoderMethod = "getCCOutOpValue";
let PrintMethod = "printSBitModifierOperand";
+ let ParserMatchClass = CCOutOperand;
}
// ARM special operands for disassembly only.
}
//===----------------------------------------------------------------------===//
-
// ARM Instruction templates.
//
}
//===----------------------------------------------------------------------===//
-//
// Thumb Instruction Format Definitions.
//
-// TI - Thumb instruction.
-
class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
InstrItinClass itin, string asm, string cstr, list<dag> pattern>
: InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
list<Predicate> Predicates = [IsThumb];
}
+// TI - Thumb instruction.
class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
: ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
class T1pIt<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
- "$lhs = $dst", pattern>;
+ "$Rn = $Rdn", pattern>;
class T1pIs<dag oops, dag iops,
InstrItinClass itin, string opc, string asm, list<dag> pattern>
// 0b0110 => Immediate, 4 bytes
// 0b1000 => Immediate, 2 bytes
// 0b0111 => Immediate, 1 byte
-class T1pIEncode<bits<3> opcode, dag oops, dag iops, AddrMode am,
- InstrItinClass itin, string opc, string asm,
- list<dag> pattern>
+class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am,
+ InstrItinClass itin, string opc, string asm,
+ list<dag> pattern>
: Thumb1pI<oops, iops, am, Size2Bytes, itin, opc, asm, "", pattern>,
T1LoadStore<0b0101, opcode> {
bits<3> Rt;
let Inst{5-3} = addr{2-0}; // Rn
let Inst{2-0} = Rt;
}
-class T1pIEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am,
- InstrItinClass itin, string opc, string asm,
- list<dag> pattern>
+class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am,
+ InstrItinClass itin, string opc, string asm,
+ list<dag> pattern>
: Thumb1pI<oops, iops, am, Size2Bytes, itin, opc, asm, "", pattern>,
T1LoadStore<opA, {opB,?,?}> {
bits<3> Rt;
InstrItinClass itin,
string opc, string asm, string cstr, list<dag> pattern>
: InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
+ bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
+ let Inst{20} = s;
+
let OutOperandList = oops;
let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
let AsmString = !strconcat(opc, "${s}${p}", asm);
let Inst{22} = 1;
let Inst{21} = W;
let Inst{20} = load;
+
+ bits<4> Rt;
+ bits<4> Rt2;
+ bits<13> addr;
+ let Inst{15-12} = Rt{3-0};
+ let Inst{11-8} = Rt2{3-0};
+ let Inst{19-16} = addr{12-9};
+ let Inst{23} = addr{8};
+ let Inst{7-0} = addr{7-0};
}
class T2sI<dag oops, dag iops, InstrItinClass itin,
let InOperandList = !con(iops, (ins pred:$p));
let AsmString = !strconcat(opc, "${p}", asm);
let Pattern = pattern;
+ let PostEncoderMethod = "VFPThumb2PostEncoder";
list<Predicate> Predicates = [HasVFP2];
}
let InOperandList = iops;
let AsmString = asm;
let Pattern = pattern;
+ let PostEncoderMethod = "VFPThumb2PostEncoder";
list<Predicate> Predicates = [HasVFP2];
}
class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
- opc, asm, "", pattern>;
+ opc, asm, "", pattern> {
+ let PostEncoderMethod = "VFPThumb2PostEncoder";
+}
// ARM VFP addrmode5 loads and stores
class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
let Inst{4} = opcod5;
}
-// Single precision unary, if no NEON
-// Same as ASuI except not available if NEON is enabled
+// Single precision unary, if no NEON. Same as ASuI except not available if
+// NEON is enabled.
class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
string asm, list<dag> pattern>
let Inst{4} = op4;
}
-// Single precision binary, if no NEON
-// Same as ASbI except not available if NEON is enabled
+// Single precision binary, if no NEON. Same as ASbI except not available if
+// NEON is enabled.
class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
dag iops, InstrItinClass itin, string opc, string asm,
list<dag> pattern>