Use doxygen comment syntax.

[oota-llvm.git] / lib / Target / ARM / ARMInstrFormats.td

diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index 2a30e777ee0ea82c18347a8a18570bcf9e72bb60..9a1e1c2bb7564ce8d345ef553f73aa34af3f8c6d 100644 (file)
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -19,24 +19,35 @@ class Format<bits<5> val> {
   bits<5> Value = val;
 }
 
-def Pseudo      : Format<1>;
-def MulFrm      : Format<2>;
-def Branch      : Format<3>;
-def BranchMisc  : Format<4>;
-
-def DPFrm       : Format<5>;
-def DPSoRegFrm  : Format<6>;
-
-def LdFrm       : Format<7>;
-def StFrm       : Format<8>;
-def LdMiscFrm   : Format<9>;
-def StMiscFrm   : Format<10>;
-def LdMulFrm    : Format<11>;
-def StMulFrm    : Format<12>;
-
-def ArithMisc   : Format<13>;
-def ThumbFrm    : Format<14>;
-def VFPFrm      : Format<15>;
+def Pseudo        : Format<0>;
+def MulFrm        : Format<1>;
+def BrFrm         : Format<2>;
+def BrMiscFrm     : Format<3>;
+
+def DPFrm         : Format<4>;
+def DPSoRegFrm    : Format<5>;
+
+def LdFrm         : Format<6>;
+def StFrm         : Format<7>;
+def LdMiscFrm     : Format<8>;
+def StMiscFrm     : Format<9>;
+def LdStMulFrm    : Format<10>;
+
+def ArithMiscFrm  : Format<11>;
+def ExtFrm        : Format<12>;
+
+def VFPUnaryFrm   : Format<13>;
+def VFPBinaryFrm  : Format<14>;
+def VFPConv1Frm   : Format<15>;
+def VFPConv2Frm   : Format<16>;
+def VFPConv3Frm   : Format<17>;
+def VFPConv4Frm   : Format<18>;
+def VFPConv5Frm   : Format<19>;
+def VFPLdStFrm    : Format<20>;
+def VFPLdStMulFrm : Format<21>;
+def VFPMiscFrm    : Format<22>;
+
+def ThumbFrm      : Format<23>;
 
 // Misc flag for data processing instructions that indicates whether
 // the instruction has a Rn register operand.
@@ -47,15 +58,13 @@ class UnaryDP  { bit isUnaryDataProc = 1; }
 // ARM Instruction templates.
 //
 
-class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
+class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
               Format f, string cstr>
   : Instruction {
   field bits<32> Inst;
 
   let Namespace = "ARM";
 
-  bits<4> Opcode = opcod;
-
   // TSFlagsFields
   AddrMode AM = am;
   bits<4> AddrModeBits = AM.Value;
@@ -78,7 +87,7 @@ class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
 }
 
 class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
-  : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
+  : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
   let OutOperandList = oops;
   let InOperandList = iops;
   let AsmString   = asm;
@@ -86,10 +95,10 @@ class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
 }
 
 // Almost all ARM instructions are predicable.
-class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
+class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
         IndexMode im, Format f, string opc, string asm, string cstr,
         list<dag> pattern>
-  : InstARM<opcod, am, sz, im, f, cstr> {
+  : InstARM<am, sz, im, f, cstr> {
   let OutOperandList = oops;
   let InOperandList = !con(iops, (ops pred:$p));
   let AsmString   = !strconcat(opc, !strconcat("${p}", asm));
@@ -100,10 +109,10 @@ class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
 // Same as I except it can optionally modify CPSR. Note it's modeled as
 // an input operand since by default it's a zero register. It will
 // become an implicit def once it's "flipped".
-class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
+class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
          IndexMode im, Format f, string opc, string asm, string cstr,
          list<dag> pattern>
-  : InstARM<opcod, am, sz, im, f, cstr> {
+  : InstARM<am, sz, im, f, cstr> {
   let OutOperandList = oops;
   let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
   let AsmString   = !strconcat(opc, !strconcat("${p}${s}", asm));
@@ -112,9 +121,9 @@ class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
 }
 
 // Special cases
-class XI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
+class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
          IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
-  : InstARM<opcod, am, sz, im, f, cstr> {
+  : InstARM<am, sz, im, f, cstr> {
   let OutOperandList = oops;
   let InOperandList = iops;
   let AsmString   = asm;
@@ -122,119 +131,80 @@ class XI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
   list<Predicate> Predicates = [IsARM];
 }
 
-class AI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI<dag oops, dag iops, Format f, string opc,
          string asm, list<dag> pattern>
-  : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
-      asm,"",pattern>;
-class AsI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+  : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
+      asm, "", pattern>;
+class AsI<dag oops, dag iops, Format f, string opc,
           string asm, list<dag> pattern>
-  : sI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
-       asm,"",pattern>;
-class AXI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+  : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
+       asm, "", pattern>;
+class AXI<dag oops, dag iops, Format f, string asm,
           list<dag> pattern>
-  : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
+  : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
        "", pattern>;
 
 // Ctrl flow instructions
-class ABLpredI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class ABI<bits<4> opcod, dag oops, dag iops, string opc,
          string asm, list<dag> pattern>
-  : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
-      asm,"",pattern> {
+  : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, opc,
+      asm, "", pattern> {
   let Inst{27-24} = opcod;
 }
-class ABLI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
-          list<dag> pattern>
-  : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
+class ABXI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
+  : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, asm,
        "", pattern> {
   let Inst{27-24} = opcod;
 }
-// FIXME: BX
-class AXIx2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
-            list<dag> pattern>
-  : XI<opcod, oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm,
+class ABXIx2<dag oops, dag iops, string asm, list<dag> pattern>
+  : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, asm,
        "", pattern>;
-class ABI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
-          list<dag> pattern>
-  : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
-       "", pattern> {
-  let Inst{27-24} = opcod;
-}
-class ABccI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
-         string asm, list<dag> pattern>
-  : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
-      asm,"",pattern> {
-  let Inst{27-24} = opcod;
-}
 
 // BR_JT instructions
-// == mov pc
-class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
-  : XI<opcod, oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc,
-       asm, "", pattern> {
-  let Inst{20}    = 0; // S Bit
-  let Inst{24-21} = opcod;
-  let Inst{27-26} = {0,0};
-}
-// == add pc
-class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
-  : XI<opcod, oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc,
-       asm, "", pattern> {
-  let Inst{20}    = 0; // S bit
-  let Inst{24-21} = opcod;
-  let Inst{27-26} = {0,0};
-}
-// == ldr pc
-class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
-  : XI<opcod, oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc,
-       asm, "", pattern> {
-  let Inst{20}    = 1; // L bit
-  let Inst{21}    = 0; // W bit
-  let Inst{22}    = 0; // B bit
-  let Inst{24}    = 1; // P bit
-  let Inst{27-26} = {0,1};
-}
-
+class JTI<dag oops, dag iops, string asm, list<dag> pattern>
+  : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm,
+       asm, "", pattern>;
 
 // addrmode1 instructions
 class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
           string asm, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
+  : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
       asm, "", pattern> {
   let Inst{24-21} = opcod;
   let Inst{27-26} = {0,0};
 }
 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
            string asm, list<dag> pattern>
-  : sI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
+  : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
        asm, "", pattern> {
   let Inst{24-21} = opcod;
   let Inst{27-26} = {0,0};
 }
 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
            list<dag> pattern>
-  : XI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
+  : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
        "", pattern> {
   let Inst{24-21} = opcod;
   let Inst{27-26} = {0,0};
 }
-class AI1x2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI1x2<dag oops, dag iops, Format f, string opc,
             string asm, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
+  : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
       asm, "", pattern>;
 
 
 // addrmode2 loads and stores
-class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI2<dag oops, dag iops, Format f, string opc,
           string asm, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
+  : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
       asm, "", pattern> {
   let Inst{27-26} = {0,1};
 }
 
 // loads
-class AI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI2ldw<dag oops, dag iops, Format f, string opc,
           string asm, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
+  : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
       asm, "", pattern> {
   let Inst{20}    = 1; // L bit
   let Inst{21}    = 0; // W bit
@@ -242,9 +212,9 @@ class AI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
   let Inst{24}    = 1; // P bit
   let Inst{27-26} = {0,1};
 }
-class AXI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+class AXI2ldw<dag oops, dag iops, Format f, string asm,
            list<dag> pattern>
-  : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
+  : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
        asm, "", pattern> {
   let Inst{20}    = 1; // L bit
   let Inst{21}    = 0; // W bit
@@ -252,9 +222,9 @@ class AXI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string asm,
   let Inst{24}    = 1; // P bit
   let Inst{27-26} = {0,1};
 }
-class AI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI2ldb<dag oops, dag iops, Format f, string opc,
           string asm, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
+  : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
       asm, "", pattern> {
   let Inst{20}    = 1; // L bit
   let Inst{21}    = 0; // W bit
@@ -262,9 +232,9 @@ class AI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
   let Inst{24}    = 1; // P bit
   let Inst{27-26} = {0,1};
 }
-class AXI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+class AXI2ldb<dag oops, dag iops, Format f, string asm,
            list<dag> pattern>
-  : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
+  : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
        asm, "", pattern> {
   let Inst{20}    = 1; // L bit
   let Inst{21}    = 0; // W bit
@@ -274,9 +244,9 @@ class AXI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
 }
 
 // stores
-class AI2stw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI2stw<dag oops, dag iops, Format f, string opc,
           string asm, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
+  : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
       asm, "", pattern> {
   let Inst{20}    = 0; // L bit
   let Inst{21}    = 0; // W bit
@@ -284,9 +254,9 @@ class AI2stw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
   let Inst{24}    = 1; // P bit
   let Inst{27-26} = {0,1};
 }
-class AXI2stw<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+class AXI2stw<dag oops, dag iops, Format f, string asm,
            list<dag> pattern>
-  : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
+  : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
        asm, "", pattern> {
   let Inst{20}    = 0; // L bit
   let Inst{21}    = 0; // W bit
@@ -294,9 +264,9 @@ class AXI2stw<bits<4> opcod, dag oops, dag iops, Format f, string asm,
   let Inst{24}    = 1; // P bit
   let Inst{27-26} = {0,1};
 }
-class AI2stb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI2stb<dag oops, dag iops, Format f, string opc,
           string asm, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
+  : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
       asm, "", pattern> {
   let Inst{20}    = 0; // L bit
   let Inst{21}    = 0; // W bit
@@ -304,9 +274,9 @@ class AI2stb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
   let Inst{24}    = 1; // P bit
   let Inst{27-26} = {0,1};
 }
-class AXI2stb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+class AXI2stb<dag oops, dag iops, Format f, string asm,
            list<dag> pattern>
-  : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
+  : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
        asm, "", pattern> {
   let Inst{20}    = 0; // L bit
   let Inst{21}    = 0; // W bit
@@ -316,9 +286,9 @@ class AXI2stb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
 }
 
 // Pre-indexed loads
-class AI2ldwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI2ldwpr<dag oops, dag iops, Format f, string opc,
             string asm, string cstr, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
+  : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
       asm, cstr, pattern> {
   let Inst{20}    = 1; // L bit
   let Inst{21}    = 1; // W bit
@@ -326,9 +296,9 @@ class AI2ldwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
   let Inst{24}    = 1; // P bit
   let Inst{27-26} = {0,1};
 }
-class AI2ldbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI2ldbpr<dag oops, dag iops, Format f, string opc,
             string asm, string cstr, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
+  : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
       asm, cstr, pattern> {
   let Inst{20}    = 1; // L bit
   let Inst{21}    = 1; // W bit
@@ -338,9 +308,9 @@ class AI2ldbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
 }
 
 // Pre-indexed stores
-class AI2stwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI2stwpr<dag oops, dag iops, Format f, string opc,
             string asm, string cstr, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
+  : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
       asm, cstr, pattern> {
   let Inst{20}    = 0; // L bit
   let Inst{21}    = 1; // W bit
@@ -348,9 +318,9 @@ class AI2stwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
   let Inst{24}    = 1; // P bit
   let Inst{27-26} = {0,1};
 }
-class AI2stbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI2stbpr<dag oops, dag iops, Format f, string opc,
             string asm, string cstr, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
+  : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
       asm, cstr, pattern> {
   let Inst{20}    = 0; // L bit
   let Inst{21}    = 1; // W bit
@@ -360,9 +330,9 @@ class AI2stbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
 }
 
 // Post-indexed loads
-class AI2ldwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI2ldwpo<dag oops, dag iops, Format f, string opc,
             string asm, string cstr, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
+  : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
       asm, cstr,pattern> {
   let Inst{20}    = 1; // L bit
   let Inst{21}    = 0; // W bit
@@ -370,9 +340,9 @@ class AI2ldwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
   let Inst{24}    = 0; // P bit
   let Inst{27-26} = {0,1};
 }
-class AI2ldbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI2ldbpo<dag oops, dag iops, Format f, string opc,
             string asm, string cstr, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
+  : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
       asm, cstr,pattern> {
   let Inst{20}    = 1; // L bit
   let Inst{21}    = 0; // W bit
@@ -382,9 +352,9 @@ class AI2ldbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
 }
 
 // Post-indexed stores
-class AI2stwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI2stwpo<dag oops, dag iops, Format f, string opc,
             string asm, string cstr, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
+  : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
       asm, cstr,pattern> {
   let Inst{20}    = 0; // L bit
   let Inst{21}    = 0; // W bit
@@ -392,9 +362,9 @@ class AI2stwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
   let Inst{24}    = 0; // P bit
   let Inst{27-26} = {0,1};
 }
-class AI2stbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI2stbpo<dag oops, dag iops, Format f, string opc,
             string asm, string cstr, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
+  : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
       asm, cstr,pattern> {
   let Inst{20}    = 0; // L bit
   let Inst{21}    = 0; // W bit
@@ -404,19 +374,19 @@ class AI2stbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
 }
 
 // addrmode3 instructions
-class AI3<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI3<dag oops, dag iops, Format f, string opc,
           string asm, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
+  : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
       asm, "", pattern>;
-class AXI3<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+class AXI3<dag oops, dag iops, Format f, string asm,
            list<dag> pattern>
-  : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
+  : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
        "", pattern>;
 
 // loads
-class AI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI3ldh<dag oops, dag iops, Format f, string opc,
           string asm, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
+  : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
       asm, "", pattern> {
   let Inst{4}     = 1;
   let Inst{5}     = 1; // H bit
@@ -426,9 +396,9 @@ class AI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
   let Inst{21}    = 0; // W bit
   let Inst{24}    = 1; // P bit
 }
-class AXI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+class AXI3ldh<dag oops, dag iops, Format f, string asm,
            list<dag> pattern>
-  : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
+  : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
        asm, "", pattern> {
   let Inst{4}     = 1;
   let Inst{5}     = 1; // H bit
@@ -438,9 +408,9 @@ class AXI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string asm,
   let Inst{21}    = 0; // W bit
   let Inst{24}    = 1; // P bit
 }
-class AI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI3ldsh<dag oops, dag iops, Format f, string opc,
           string asm, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
+  : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
       asm, "", pattern> {
   let Inst{4}     = 1;
   let Inst{5}     = 1; // H bit
@@ -450,9 +420,9 @@ class AI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
   let Inst{21}    = 0; // W bit
   let Inst{24}    = 1; // P bit
 }
-class AXI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+class AXI3ldsh<dag oops, dag iops, Format f, string asm,
            list<dag> pattern>
-  : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
+  : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
        asm, "", pattern> {
   let Inst{4}     = 1;
   let Inst{5}     = 1; // H bit
@@ -462,9 +432,9 @@ class AXI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string asm,
   let Inst{21}    = 0; // W bit
   let Inst{24}    = 1; // P bit
 }
-class AI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI3ldsb<dag oops, dag iops, Format f, string opc,
           string asm, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
+  : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
       asm, "", pattern> {
   let Inst{4}     = 1;
   let Inst{5}     = 0; // H bit
@@ -474,9 +444,9 @@ class AI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
   let Inst{21}    = 0; // W bit
   let Inst{24}    = 1; // P bit
 }
-class AXI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+class AXI3ldsb<dag oops, dag iops, Format f, string asm,
            list<dag> pattern>
-  : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
+  : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
        asm, "", pattern> {
   let Inst{4}     = 1;
   let Inst{5}     = 0; // H bit
@@ -486,9 +456,9 @@ class AXI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
   let Inst{21}    = 0; // W bit
   let Inst{24}    = 1; // P bit
 }
-class AI3ldd<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI3ldd<dag oops, dag iops, Format f, string opc,
           string asm, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
+  : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
       asm, "", pattern> {
   let Inst{4}     = 1;
   let Inst{5}     = 0; // H bit
@@ -500,9 +470,9 @@ class AI3ldd<bits<4> opcod, dag oops, dag iops, Format f, string opc,
 }
 
 // stores
-class AI3sth<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI3sth<dag oops, dag iops, Format f, string opc,
           string asm, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
+  : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
       asm, "", pattern> {
   let Inst{4}     = 1;
   let Inst{5}     = 1; // H bit
@@ -512,9 +482,9 @@ class AI3sth<bits<4> opcod, dag oops, dag iops, Format f, string opc,
   let Inst{21}    = 0; // W bit
   let Inst{24}    = 1; // P bit
 }
-class AXI3sth<bits<4> opcod, dag oops, dag iops, Format f, string asm,
+class AXI3sth<dag oops, dag iops, Format f, string asm,
            list<dag> pattern>
-  : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
+  : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
        asm, "", pattern> {
   let Inst{4}     = 1;
   let Inst{5}     = 1; // H bit
@@ -524,9 +494,9 @@ class AXI3sth<bits<4> opcod, dag oops, dag iops, Format f, string asm,
   let Inst{21}    = 0; // W bit
   let Inst{24}    = 1; // P bit
 }
-class AI3std<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI3std<dag oops, dag iops, Format f, string opc,
           string asm, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
+  : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
       asm, "", pattern> {
   let Inst{4}     = 1;
   let Inst{5}     = 1; // H bit
@@ -538,9 +508,9 @@ class AI3std<bits<4> opcod, dag oops, dag iops, Format f, string opc,
 }
 
 // Pre-indexed loads
-class AI3ldhpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI3ldhpr<dag oops, dag iops, Format f, string opc,
             string asm, string cstr, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
+  : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
       asm, cstr, pattern> {
   let Inst{4}     = 1;
   let Inst{5}     = 1; // H bit
@@ -550,9 +520,9 @@ class AI3ldhpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
   let Inst{21}    = 1; // W bit
   let Inst{24}    = 1; // P bit
 }
-class AI3ldshpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI3ldshpr<dag oops, dag iops, Format f, string opc,
             string asm, string cstr, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
+  : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
       asm, cstr, pattern> {
   let Inst{4}     = 1;
   let Inst{5}     = 1; // H bit
@@ -562,9 +532,9 @@ class AI3ldshpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
   let Inst{21}    = 1; // W bit
   let Inst{24}    = 1; // P bit
 }
-class AI3ldsbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI3ldsbpr<dag oops, dag iops, Format f, string opc,
             string asm, string cstr, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
+  : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
       asm, cstr, pattern> {
   let Inst{4}     = 1;
   let Inst{5}     = 0; // H bit
@@ -576,9 +546,9 @@ class AI3ldsbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
 }
 
 // Pre-indexed stores
-class AI3sthpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI3sthpr<dag oops, dag iops, Format f, string opc,
             string asm, string cstr, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
+  : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
       asm, cstr, pattern> {
   let Inst{4}     = 1;
   let Inst{5}     = 1; // H bit
@@ -590,9 +560,9 @@ class AI3sthpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
 }
 
 // Post-indexed loads
-class AI3ldhpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI3ldhpo<dag oops, dag iops, Format f, string opc,
             string asm, string cstr, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
+  : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
       asm, cstr,pattern> {
   let Inst{4}     = 1;
   let Inst{5}     = 1; // H bit
@@ -602,9 +572,9 @@ class AI3ldhpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
   let Inst{21}    = 1; // W bit
   let Inst{24}    = 0; // P bit
 }
-class AI3ldshpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI3ldshpo<dag oops, dag iops, Format f, string opc,
             string asm, string cstr, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
+  : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
       asm, cstr,pattern> {
   let Inst{4}     = 1;
   let Inst{5}     = 1; // H bit
@@ -614,9 +584,9 @@ class AI3ldshpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
   let Inst{21}    = 1; // W bit
   let Inst{24}    = 0; // P bit
 }
-class AI3ldsbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI3ldsbpo<dag oops, dag iops, Format f, string opc,
             string asm, string cstr, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
+  : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
       asm, cstr,pattern> {
   let Inst{4}     = 1;
   let Inst{5}     = 0; // H bit
@@ -628,9 +598,9 @@ class AI3ldsbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
 }
 
 // Post-indexed stores
-class AI3sthpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+class AI3sthpo<dag oops, dag iops, Format f, string opc,
             string asm, string cstr, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
+  : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
       asm, cstr,pattern> {
   let Inst{4}     = 1;
   let Inst{5}     = 1; // H bit
@@ -643,30 +613,15 @@ class AI3sthpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
 
 
 // addrmode4 instructions
-class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc,
-          string asm, list<dag> pattern>
-  : I<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc,
-      asm, "", pattern> {
-  let Inst{25-27} = {0,0,1};
-}
-class AXI4ld<bits<4> opcod, dag oops, dag iops, Format f, string asm,
-           list<dag> pattern>
-  : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
+class AXI4ld<dag oops, dag iops, Format f, string asm, list<dag> pattern>
+  : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
        "", pattern> {
   let Inst{20}    = 1; // L bit
   let Inst{22}    = 0; // S bit
   let Inst{27-25} = 0b100;
 }
-class AXI4ldpc<bits<4> opcod, dag oops, dag iops, Format f, string asm,
-           list<dag> pattern>
-  : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
-       "", pattern> {
-  let Inst{20}    = 1; // L bit
-  let Inst{27-25} = 0b100;
-}
-class AXI4st<bits<4> opcod, dag oops, dag iops, Format f, string asm,
-           list<dag> pattern>
-  : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
+class AXI4st<dag oops, dag iops, Format f, string asm, list<dag> pattern>
+  : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
        "", pattern> {
   let Inst{20}    = 0; // L bit
   let Inst{22}    = 0; // S bit
@@ -674,41 +629,58 @@ class AXI4st<bits<4> opcod, dag oops, dag iops, Format f, string asm,
 }
 
 // Unsigned multiply, multiply-accumulate instructions.
-class AMul1I<bits<7> mulopc, dag oops, dag iops, string opc,
+class AMul1I<bits<7> opcod, dag oops, dag iops, string opc,
          string asm, list<dag> pattern>
-  : I<0, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
-      asm,"",pattern> {
+  : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
+      asm, "", pattern> {
   let Inst{7-4}   = 0b1001;
   let Inst{20}    = 0; // S bit
-  let Inst{27-21} = mulopc;
+  let Inst{27-21} = opcod;
 }
-class AsMul1I<bits<7> mulopc, dag oops, dag iops, string opc,
+class AsMul1I<bits<7> opcod, dag oops, dag iops, string opc,
           string asm, list<dag> pattern>
-  : sI<0, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
-       asm,"",pattern> {
+  : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
+       asm, "", pattern> {
   let Inst{7-4}   = 0b1001;
-  let Inst{27-21} = mulopc;
+  let Inst{27-21} = opcod;
 }
 
 // Most significant word multiply
-class AMul2I<bits<7> mulopc, dag oops, dag iops, string opc,
+class AMul2I<bits<7> opcod, dag oops, dag iops, string opc,
          string asm, list<dag> pattern>
-  : I<0, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
-      asm,"",pattern> {
+  : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
+      asm, "", pattern> {
   let Inst{7-4}   = 0b1001;
   let Inst{20}    = 1;
-  let Inst{27-21} = mulopc;
+  let Inst{27-21} = opcod;
 }
 
 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
-class AMulxyI<bits<7> mulopc, dag oops, dag iops, string opc,
+class AMulxyI<bits<7> opcod, dag oops, dag iops, string opc,
          string asm, list<dag> pattern>
-  : I<0, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
-      asm,"",pattern> {
+  : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
+      asm, "", pattern> {
   let Inst{4}     = 0;
   let Inst{7}     = 1;
   let Inst{20}    = 0;
-  let Inst{27-21} = mulopc;
+  let Inst{27-21} = opcod;
+}
+
+// Extend instructions.
+class AExtI<bits<8> opcod, dag oops, dag iops, string opc,
+            string asm, list<dag> pattern>
+  : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, opc,
+      asm, "", pattern> {
+  let Inst{7-4}   = 0b0111;
+  let Inst{27-20} = opcod;
+}
+
+// Misc Arithmetic instructions.
+class AMiscA1I<bits<8> opcod, dag oops, dag iops, string opc,
+               string asm, list<dag> pattern>
+  : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, opc,
+      asm, "", pattern> {
+  let Inst{27-20} = opcod;
 }
 
 //===----------------------------------------------------------------------===//
@@ -734,8 +706,7 @@ class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
 
 class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
              string asm, string cstr, list<dag> pattern>
-  // FIXME: Set all opcodes to 0 for now.
-  : InstARM<0, am, sz, IndexModeNone, ThumbFrm, cstr> {
+  : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> {
   let OutOperandList = outs;
   let InOperandList = ins;
   let AsmString   = asm;
@@ -769,6 +740,123 @@ class TJTI<dag outs, dag ins, string asm, list<dag> pattern>
 
 //===----------------------------------------------------------------------===//
 
+//===----------------------------------------------------------------------===//
+// ARM VFP Instruction templates.
+//
+
+// ARM VFP addrmode5 loads and stores
+class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
+           string opc, string asm, list<dag> pattern>
+  : I<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
+      VFPLdStFrm, opc, asm, "", pattern> {
+  // TODO: Mark the instructions with the appropriate subtarget info.
+  let Inst{27-24} = opcod1;
+  let Inst{21-20} = opcod2;
+  let Inst{11-8}  = 0b1011;
+}
+
+class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
+           string opc, string asm, list<dag> pattern>
+  : I<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
+      VFPLdStFrm, opc, asm, "", pattern> {
+  // TODO: Mark the instructions with the appropriate subtarget info.
+  let Inst{27-24} = opcod1;
+  let Inst{21-20} = opcod2;
+  let Inst{11-8}  = 0b1010;
+}
+
+// Load / store multiple
+class AXSI5<dag oops, dag iops, string asm, list<dag> pattern>
+  : XI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
+       VFPLdStMulFrm, asm, "", pattern> {
+  // TODO: Mark the instructions with the appropriate subtarget info.
+  let Inst{27-25} = 0b110;
+  let Inst{11-8}  = 0b1011;
+}
+
+class AXDI5<dag oops, dag iops, string asm, list<dag> pattern>
+  : XI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
+       VFPLdStMulFrm, asm, "", pattern> {
+  // TODO: Mark the instructions with the appropriate subtarget info.
+  let Inst{27-25} = 0b110;
+  let Inst{11-8}  = 0b1010;
+}
+
+
+// Double precision, unary
+class ADuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops,
+           string opc, string asm, list<dag> pattern>
+  : AI<oops, iops, VFPUnaryFrm, opc, asm, pattern> {
+  let Inst{27-20} = opcod1;
+  let Inst{19-16} = opcod2;
+  let Inst{11-8}  = 0b1011;
+  let Inst{7-4}   = opcod3;
+}
+
+// Double precision, binary
+class ADbI<bits<8> opcod, dag oops, dag iops, string opc,
+           string asm, list<dag> pattern>
+  : AI<oops, iops, VFPBinaryFrm, opc, asm, pattern> {
+  let Inst{27-20} = opcod;
+  let Inst{11-8}  = 0b1011;
+}
+
+// Single precision, unary
+class ASuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops,
+           string opc, string asm, list<dag> pattern>
+  : AI<oops, iops, VFPUnaryFrm, opc, asm, pattern> {
+  // Bits 22 (D bit) and 5 (M bit) will be changed during instruction encoding.
+  let Inst{27-20} = opcod1;
+  let Inst{19-16} = opcod2;
+  let Inst{11-8}  = 0b1010;
+  let Inst{7-4}   = opcod3;
+}
+
+// Single precision, binary
+class ASbI<bits<8> opcod, dag oops, dag iops, string opc,
+           string asm, list<dag> pattern>
+  : AI<oops, iops, VFPBinaryFrm, opc, asm, pattern> {
+  // Bit 22 (D bit) can be changed during instruction encoding.
+  let Inst{27-20} = opcod;
+  let Inst{11-8}  = 0b1010;
+}
+
+// VFP conversion instructions
+class AVConv1I<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3,
+               dag oops, dag iops, string opc, string asm, list<dag> pattern>
+  : AI<oops, iops, VFPConv1Frm, opc, asm, pattern> {
+  let Inst{27-20} = opcod1;
+  let Inst{19-16} = opcod2;
+  let Inst{11-8}  = opcod3;
+  let Inst{6}     = 1;
+}
+
+class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
+             string opc, string asm, list<dag> pattern>
+  : AI<oops, iops, f, opc, asm, pattern> {
+  let Inst{27-20} = opcod1;
+  let Inst{11-8}  = opcod2;
+  let Inst{4}     = 1;
+}
+
+class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
+              string asm, list<dag> pattern>
+  : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, opc, asm, pattern>;
+
+class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
+              string asm, list<dag> pattern>
+  : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, opc, asm, pattern>;
+
+class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
+              string asm, list<dag> pattern>
+  : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, opc, asm, pattern>;
+
+class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
+              string asm, list<dag> pattern>
+  : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, opc, asm, pattern>;
+
+//===----------------------------------------------------------------------===//
+
 
 // ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
 class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {