Use doxygen comment syntax.

[oota-llvm.git] / lib / Target / ARM / ARMInstrFormats.td

diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index c898acae041ab26e074f1ae48fbf687a466e1341..9a1e1c2bb7564ce8d345ef553f73aa34af3f8c6d 100644 (file)
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -19,27 +19,35 @@ class Format<bits<5> val> {
   bits<5> Value = val;
 }
 
-def Pseudo      : Format<1>;
-def MulFrm      : Format<2>;
-def BrFrm       : Format<3>;
-def BrMiscFrm   : Format<4>;
-
-def DPFrm       : Format<5>;
-def DPSoRegFrm  : Format<6>;
-
-def LdFrm       : Format<7>;
-def StFrm       : Format<8>;
-def LdMiscFrm   : Format<9>;
-def StMiscFrm   : Format<10>;
-def LdMulFrm    : Format<11>;
-def StMulFrm    : Format<12>;
-
-def ArithMiscFrm: Format<13>;
-def ExtFrm      : Format<14>;
-def VFPFrm      : Format<15>;
-def VFPUnaryFrm : Format<16>;
-def VFPBinaryFrm: Format<17>;
-def ThumbFrm    : Format<18>;
+def Pseudo        : Format<0>;
+def MulFrm        : Format<1>;
+def BrFrm         : Format<2>;
+def BrMiscFrm     : Format<3>;
+
+def DPFrm         : Format<4>;
+def DPSoRegFrm    : Format<5>;
+
+def LdFrm         : Format<6>;
+def StFrm         : Format<7>;
+def LdMiscFrm     : Format<8>;
+def StMiscFrm     : Format<9>;
+def LdStMulFrm    : Format<10>;
+
+def ArithMiscFrm  : Format<11>;
+def ExtFrm        : Format<12>;
+
+def VFPUnaryFrm   : Format<13>;
+def VFPBinaryFrm  : Format<14>;
+def VFPConv1Frm   : Format<15>;
+def VFPConv2Frm   : Format<16>;
+def VFPConv3Frm   : Format<17>;
+def VFPConv4Frm   : Format<18>;
+def VFPConv5Frm   : Format<19>;
+def VFPLdStFrm    : Format<20>;
+def VFPLdStMulFrm : Format<21>;
+def VFPMiscFrm    : Format<22>;
+
+def ThumbFrm      : Format<23>;
 
 // Misc flag for data processing instructions that indicates whether
 // the instruction has a Rn register operand.
@@ -736,30 +744,45 @@ class TJTI<dag outs, dag ins, string asm, list<dag> pattern>
 // ARM VFP Instruction templates.
 //
 
-// ARM Float Instruction
-class ASI<dag oops, dag iops, string opc, string asm, list<dag> pattern>
-  : AI<oops, iops, VFPFrm, opc, asm, pattern> {
+// ARM VFP addrmode5 loads and stores
+class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
+           string opc, string asm, list<dag> pattern>
+  : I<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
+      VFPLdStFrm, opc, asm, "", pattern> {
   // TODO: Mark the instructions with the appropriate subtarget info.
+  let Inst{27-24} = opcod1;
+  let Inst{21-20} = opcod2;
+  let Inst{11-8}  = 0b1011;
 }
 
-class ASI5<dag oops, dag iops, string opc, string asm, list<dag> pattern>
+class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
+           string opc, string asm, list<dag> pattern>
   : I<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
-      VFPFrm, opc, asm, "", pattern> {
+      VFPLdStFrm, opc, asm, "", pattern> {
   // TODO: Mark the instructions with the appropriate subtarget info.
+  let Inst{27-24} = opcod1;
+  let Inst{21-20} = opcod2;
+  let Inst{11-8}  = 0b1010;
 }
 
-// ARM Double Instruction
-class ADI<dag oops, dag iops, string opc, string asm, list<dag> pattern>
-  : AI<oops, iops, VFPFrm, opc, asm, pattern> {
+// Load / store multiple
+class AXSI5<dag oops, dag iops, string asm, list<dag> pattern>
+  : XI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
+       VFPLdStMulFrm, asm, "", pattern> {
   // TODO: Mark the instructions with the appropriate subtarget info.
+  let Inst{27-25} = 0b110;
+  let Inst{11-8}  = 0b1011;
 }
 
-class ADI5<dag oops, dag iops, string opc, string asm, list<dag> pattern>
-  : I<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
-      VFPFrm, opc, asm, "", pattern> {
+class AXDI5<dag oops, dag iops, string asm, list<dag> pattern>
+  : XI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
+       VFPLdStMulFrm, asm, "", pattern> {
   // TODO: Mark the instructions with the appropriate subtarget info.
+  let Inst{27-25} = 0b110;
+  let Inst{11-8}  = 0b1010;
 }
 
+
 // Double precision, unary
 class ADuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops,
            string opc, string asm, list<dag> pattern>
@@ -798,31 +821,39 @@ class ASbI<bits<8> opcod, dag oops, dag iops, string opc,
   let Inst{11-8}  = 0b1010;
 }
 
-// Special cases.
-class AXSI<dag oops, dag iops, string asm, list<dag> pattern>
-  : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone,
-       VFPFrm, asm, "", pattern> {
-  // TODO: Mark the instructions with the appropriate subtarget info.
+// VFP conversion instructions
+class AVConv1I<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3,
+               dag oops, dag iops, string opc, string asm, list<dag> pattern>
+  : AI<oops, iops, VFPConv1Frm, opc, asm, pattern> {
+  let Inst{27-20} = opcod1;
+  let Inst{19-16} = opcod2;
+  let Inst{11-8}  = opcod3;
+  let Inst{6}     = 1;
 }
 
-class AXSI5<dag oops, dag iops, string asm, list<dag> pattern>
-  : XI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
-       VFPFrm, asm, "", pattern> {
-  // TODO: Mark the instructions with the appropriate subtarget info.
+class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
+             string opc, string asm, list<dag> pattern>
+  : AI<oops, iops, f, opc, asm, pattern> {
+  let Inst{27-20} = opcod1;
+  let Inst{11-8}  = opcod2;
+  let Inst{4}     = 1;
 }
 
-class AXDI<dag oops, dag iops, string asm, list<dag> pattern>
-  : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone,
-       VFPFrm, asm, "", pattern> {
-  // TODO: Mark the instructions with the appropriate subtarget info.
-}
+class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
+              string asm, list<dag> pattern>
+  : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, opc, asm, pattern>;
 
-class AXDI5<dag oops, dag iops, string asm, list<dag> pattern>
-  : XI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
-       VFPFrm, asm, "", pattern> {
-  // TODO: Mark the instructions with the appropriate subtarget info.
-}
+class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
+              string asm, list<dag> pattern>
+  : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, opc, asm, pattern>;
+
+class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
+              string asm, list<dag> pattern>
+  : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, opc, asm, pattern>;
 
+class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
+              string asm, list<dag> pattern>
+  : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, opc, asm, pattern>;
 
 //===----------------------------------------------------------------------===//