bits<5> Value = val;
}
-def Pseudo : Format<1>;
-def MulFrm : Format<2>;
-def BrFrm : Format<3>;
-def BrMiscFrm : Format<4>;
-
-def DPFrm : Format<5>;
-def DPSoRegFrm : Format<6>;
-
-def LdFrm : Format<7>;
-def StFrm : Format<8>;
-def LdMiscFrm : Format<9>;
-def StMiscFrm : Format<10>;
-def LdMulFrm : Format<11>;
-def StMulFrm : Format<12>;
-
-def ArithMiscFrm: Format<13>;
-def ExtFrm : Format<14>;
-def ThumbFrm : Format<15>;
-def VFPFrm : Format<16>;
+def Pseudo : Format<0>;
+def MulFrm : Format<1>;
+def BrFrm : Format<2>;
+def BrMiscFrm : Format<3>;
+
+def DPFrm : Format<4>;
+def DPSoRegFrm : Format<5>;
+
+def LdFrm : Format<6>;
+def StFrm : Format<7>;
+def LdMiscFrm : Format<8>;
+def StMiscFrm : Format<9>;
+def LdStMulFrm : Format<10>;
+
+def ArithMiscFrm : Format<11>;
+def ExtFrm : Format<12>;
+
+def VFPUnaryFrm : Format<13>;
+def VFPBinaryFrm : Format<14>;
+def VFPConv1Frm : Format<15>;
+def VFPConv2Frm : Format<16>;
+def VFPConv3Frm : Format<17>;
+def VFPConv4Frm : Format<18>;
+def VFPConv5Frm : Format<19>;
+def VFPLdStFrm : Format<20>;
+def VFPLdStMulFrm : Format<21>;
+def VFPMiscFrm : Format<22>;
+
+def ThumbFrm : Format<23>;
// Misc flag for data processing instructions that indicates whether
// the instruction has a Rn register operand.
"", pattern>;
// BR_JT instructions
-// == mov pc
-class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
+class JTI<dag oops, dag iops, string asm, list<dag> pattern>
: XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm,
- asm, "", pattern> {
- let Inst{20} = 0; // S Bit
- let Inst{24-21} = opcod;
- let Inst{27-26} = {0,0};
-}
-// == add pc
-class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
- : XI<oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BrMiscFrm,
- asm, "", pattern> {
- let Inst{20} = 0; // S bit
- let Inst{24-21} = opcod;
- let Inst{27-26} = {0,0};
-}
-// == ldr pc
-class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
- : XI<oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BrMiscFrm,
- asm, "", pattern> {
- let Inst{20} = 1; // L bit
- let Inst{21} = 0; // W bit
- let Inst{22} = 0; // B bit
- let Inst{24} = 1; // P bit
- let Inst{27-26} = {0,1};
-}
-
+ asm, "", pattern>;
// addrmode1 instructions
class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
let Inst{27-20} = opcod;
}
+// Misc Arithmetic instructions.
+class AMiscA1I<bits<8> opcod, dag oops, dag iops, string opc,
+ string asm, list<dag> pattern>
+ : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, opc,
+ asm, "", pattern> {
+ let Inst{27-20} = opcod;
+}
+
//===----------------------------------------------------------------------===//
// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
//===----------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
+// ARM VFP Instruction templates.
+//
+
+// ARM VFP addrmode5 loads and stores
+class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
+ string opc, string asm, list<dag> pattern>
+ : I<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
+ VFPLdStFrm, opc, asm, "", pattern> {
+ // TODO: Mark the instructions with the appropriate subtarget info.
+ let Inst{27-24} = opcod1;
+ let Inst{21-20} = opcod2;
+ let Inst{11-8} = 0b1011;
+}
+
+class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
+ string opc, string asm, list<dag> pattern>
+ : I<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
+ VFPLdStFrm, opc, asm, "", pattern> {
+ // TODO: Mark the instructions with the appropriate subtarget info.
+ let Inst{27-24} = opcod1;
+ let Inst{21-20} = opcod2;
+ let Inst{11-8} = 0b1010;
+}
+
+// Load / store multiple
+class AXSI5<dag oops, dag iops, string asm, list<dag> pattern>
+ : XI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
+ VFPLdStMulFrm, asm, "", pattern> {
+ // TODO: Mark the instructions with the appropriate subtarget info.
+ let Inst{27-25} = 0b110;
+ let Inst{11-8} = 0b1011;
+}
+
+class AXDI5<dag oops, dag iops, string asm, list<dag> pattern>
+ : XI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
+ VFPLdStMulFrm, asm, "", pattern> {
+ // TODO: Mark the instructions with the appropriate subtarget info.
+ let Inst{27-25} = 0b110;
+ let Inst{11-8} = 0b1010;
+}
+
+
+// Double precision, unary
+class ADuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops,
+ string opc, string asm, list<dag> pattern>
+ : AI<oops, iops, VFPUnaryFrm, opc, asm, pattern> {
+ let Inst{27-20} = opcod1;
+ let Inst{19-16} = opcod2;
+ let Inst{11-8} = 0b1011;
+ let Inst{7-4} = opcod3;
+}
+
+// Double precision, binary
+class ADbI<bits<8> opcod, dag oops, dag iops, string opc,
+ string asm, list<dag> pattern>
+ : AI<oops, iops, VFPBinaryFrm, opc, asm, pattern> {
+ let Inst{27-20} = opcod;
+ let Inst{11-8} = 0b1011;
+}
+
+// Single precision, unary
+class ASuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops,
+ string opc, string asm, list<dag> pattern>
+ : AI<oops, iops, VFPUnaryFrm, opc, asm, pattern> {
+ // Bits 22 (D bit) and 5 (M bit) will be changed during instruction encoding.
+ let Inst{27-20} = opcod1;
+ let Inst{19-16} = opcod2;
+ let Inst{11-8} = 0b1010;
+ let Inst{7-4} = opcod3;
+}
+
+// Single precision, binary
+class ASbI<bits<8> opcod, dag oops, dag iops, string opc,
+ string asm, list<dag> pattern>
+ : AI<oops, iops, VFPBinaryFrm, opc, asm, pattern> {
+ // Bit 22 (D bit) can be changed during instruction encoding.
+ let Inst{27-20} = opcod;
+ let Inst{11-8} = 0b1010;
+}
+
+// VFP conversion instructions
+class AVConv1I<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3,
+ dag oops, dag iops, string opc, string asm, list<dag> pattern>
+ : AI<oops, iops, VFPConv1Frm, opc, asm, pattern> {
+ let Inst{27-20} = opcod1;
+ let Inst{19-16} = opcod2;
+ let Inst{11-8} = opcod3;
+ let Inst{6} = 1;
+}
+
+class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
+ string opc, string asm, list<dag> pattern>
+ : AI<oops, iops, f, opc, asm, pattern> {
+ let Inst{27-20} = opcod1;
+ let Inst{11-8} = opcod2;
+ let Inst{4} = 1;
+}
+
+class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
+ string asm, list<dag> pattern>
+ : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, opc, asm, pattern>;
+
+class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
+ string asm, list<dag> pattern>
+ : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, opc, asm, pattern>;
+
+class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
+ string asm, list<dag> pattern>
+ : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, opc, asm, pattern>;
+
+class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
+ string asm, list<dag> pattern>
+ : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, opc, asm, pattern>;
+
+//===----------------------------------------------------------------------===//
+
// ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
projects / oota-llvm.git / blobdiff