#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
-#include "llvm/Target/TargetAsmInfo.h"
+#include "llvm/MC/MCAsmInfo.h"
#include "llvm/Support/CommandLine.h"
using namespace llvm;
ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
- : ARMBaseInstrInfo(STI), RI(*this, STI) {
+ : RI(*this, STI), Subtarget(STI) {
}
-unsigned ARMInstrInfo::
-getUnindexedOpcode(unsigned Opc) const {
+unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
switch (Opc) {
default: break;
case ARM::LDR_PRE:
return 0;
}
-unsigned ARMInstrInfo::
-getOpcode(ARMII::Op Op) const {
- switch (Op) {
- case ARMII::ADDri: return ARM::ADDri;
- case ARMII::ADDrs: return ARM::ADDrs;
- case ARMII::ADDrr: return ARM::ADDrr;
- case ARMII::LDRri: return 0;
- case ARMII::MOVr: return ARM::MOVr;
- case ARMII::STRri: return 0;
- case ARMII::SUBri: return ARM::SUBri;
- case ARMII::SUBrs: return ARM::SUBrs;
- case ARMII::SUBrr: return ARM::SUBrr;
- default:
- break;
- }
-
- return 0;
-}
-
-bool ARMInstrInfo::
-BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
+bool ARMInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
if (MBB.empty()) return false;
switch (MBB.back().getOpcode()) {
MI->getOperand(0).setReg(DestReg);
MBB.insert(I, MI);
}
+