#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
-#include "llvm/Target/TargetAsmInfo.h"
-#include "llvm/Support/CommandLine.h"
+#include "llvm/MC/MCAsmInfo.h"
using namespace llvm;
ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
: ARMBaseInstrInfo(STI), RI(*this, STI) {
}
-unsigned ARMInstrInfo::
-getUnindexedOpcode(unsigned Opc) const {
+unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
switch (Opc) {
default: break;
case ARM::LDR_PRE:
return 0;
}
-unsigned ARMInstrInfo::
-getOpcode(ARMII::Op Op) const {
- switch (Op) {
- case ARMII::ADDri: return ARM::ADDri;
- case ARMII::MOVr: return ARM::MOVr;
- case ARMII::SUBri: return ARM::SUBri;
- default:
- break;
- }
-
- return 0;
-}
-
-bool ARMInstrInfo::
-BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
+bool ARMInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
if (MBB.empty()) return false;
switch (MBB.back().getOpcode()) {
case ARM::BX_RET: // Return.
case ARM::LDM_RET:
case ARM::B:
+ case ARM::BRIND:
case ARM::BR_JTr: // Jumptable branch.
case ARM::BR_JTm: // Jumptable branch through mem.
case ARM::BR_JTadd: // Jumptable branch add to pc.
MI->getOperand(0).setReg(DestReg);
MBB.insert(I, MI);
}
+