add float -> double and double -> float conversion

[oota-llvm.git] / lib / Target / ARM / ARMInstrInfo.td

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 55128de930d54912bb21710e9ddf0530126cb0f3..9d4649a558985fadad6f6858ecd6b125bf82b412 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -74,11 +74,17 @@ def armbr          : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag]>;
 def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
 def armcmp       : SDNode<"ARMISD::CMP",  SDTVoidBinOp, [SDNPOutFlag]>;
 
-def armfsitos    : SDNode<"ARMISD::FSITOS", SDTUnaryOp>;
+def armfsitos      : SDNode<"ARMISD::FSITOS", SDTUnaryOp>;
 def armfsitod      : SDNode<"ARMISD::FSITOD", SDTUnaryOp>;
+def armfuitos      : SDNode<"ARMISD::FUITOS", SDTUnaryOp>;
+def armfuitod      : SDNode<"ARMISD::FUITOD", SDTUnaryOp>;
 
 def SDTarmfmrrd    : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>, SDTCisFP<2>]>;
-def armfmrrd       : SDNode<"ARMISD::FMRRD", SDTarmfmrrd, [SDNPHasChain, SDNPOutFlag]>;
+def armfmrrd       : SDNode<"ARMISD::FMRRD", SDTarmfmrrd,
+                            [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
+
+def SDTarmfmdrr    : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisInt<1>, SDTCisInt<2>]>;
+def armfmdrr       : SDNode<"ARMISD::FMDRR", SDTarmfmdrr, []>;
 
 def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
                             "!ADJCALLSTACKUP $amt",
@@ -100,10 +106,6 @@ def ldr   : InstARM<(ops IntRegs:$dst, memri:$addr),
                      "ldr $dst, $addr",
                      [(set IntRegs:$dst, (load iaddr:$addr))]>;
 
-def FLDS  : InstARM<(ops FPRegs:$dst, IntRegs:$addr),
-                     "flds $dst, $addr",
-                     [(set FPRegs:$dst, (load IntRegs:$addr))]>;
-
 def str  : InstARM<(ops IntRegs:$src, memri:$addr),
                     "str $src, $addr",
                     [(store IntRegs:$src, iaddr:$addr)]>;
@@ -115,6 +117,14 @@ def ADD     : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
                        "add $dst, $a, $b",
                       [(set IntRegs:$dst, (add IntRegs:$a, addr_mode1:$b))]>;
 
+def ADCS    : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
+                       "adcs $dst, $a, $b",
+                      [(set IntRegs:$dst, (adde IntRegs:$a, addr_mode1:$b))]>;
+
+def ADDS    : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
+                       "adds $dst, $a, $b",
+                      [(set IntRegs:$dst, (addc IntRegs:$a, addr_mode1:$b))]>;
+
 // "LEA" forms of add
 def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
                         "add $dst, ${addr:arith}",
@@ -175,8 +185,50 @@ def FMRS    : InstARM<(ops IntRegs:$dst, FPRegs:$src),
 def FMRRD   : InstARM<(ops IntRegs:$i0, IntRegs:$i1, DFPRegs:$src),
                        "fmrrd $i0, $i1, $src", [(armfmrrd IntRegs:$i0, IntRegs:$i1, DFPRegs:$src)]>;
 
+def FMDRR   : InstARM<(ops DFPRegs:$dst, IntRegs:$i0, IntRegs:$i1),
+                       "fmdrr $dst, $i0, $i1", [(set DFPRegs:$dst, (armfmdrr IntRegs:$i0, IntRegs:$i1))]>;
+
 def FSITOS  : InstARM<(ops FPRegs:$dst, FPRegs:$src),
                        "fsitos $dst, $src", [(set FPRegs:$dst, (armfsitos FPRegs:$src))]>;
 
 def FSITOD  : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
                        "fsitod $dst, $src", [(set DFPRegs:$dst, (armfsitod FPRegs:$src))]>;
+
+def FUITOS  : InstARM<(ops FPRegs:$dst, FPRegs:$src),
+                       "fuitos $dst, $src", [(set FPRegs:$dst, (armfuitos FPRegs:$src))]>;
+
+def FUITOD  : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
+                       "fuitod $dst, $src", [(set DFPRegs:$dst, (armfuitod FPRegs:$src))]>;
+
+def FCVTDS  : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
+                       "fcvtds $dst, $src", [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
+
+def FCVTSD  : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
+                       "fcvtsd $dst, $src", [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
+
+// Floating Point Arithmetic
+def FADDS   : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
+                       "fadds $dst, $a, $b",
+                      [(set FPRegs:$dst, (fadd FPRegs:$a, FPRegs:$b))]>;
+
+def FADDD   : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
+                       "faddd $dst, $a, $b",
+                      [(set DFPRegs:$dst, (fadd DFPRegs:$a, DFPRegs:$b))]>;
+
+def FMULS   : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
+                       "fmuls $dst, $a, $b",
+                      [(set FPRegs:$dst, (fmul FPRegs:$a, FPRegs:$b))]>;
+
+def FMULD   : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
+                       "fmuld $dst, $a, $b",
+                      [(set DFPRegs:$dst, (fmul DFPRegs:$a, DFPRegs:$b))]>;
+
+
+// Floating Point Load
+def FLDS  : InstARM<(ops FPRegs:$dst, IntRegs:$addr),
+                     "flds $dst, $addr",
+                     [(set FPRegs:$dst, (load IntRegs:$addr))]>;
+
+def FLDD  : InstARM<(ops DFPRegs:$dst, IntRegs:$addr),
+                     "fldd $dst, $addr",
+                     [(set DFPRegs:$dst, (load IntRegs:$addr))]>;