InstrItinClass itin, string OpcodeStr, string Dt,
ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
: N3V<op24, op23, op21_20, op11_8, 0, op4,
- (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), N3RegFrm, itin,
- OpcodeStr, Dt, "$Dd, $Dn, $Dm", "",
- [(set DPR:$Dd, (ResTy (OpNode (OpTy DPR:$Dn), (OpTy DPR:$Dm))))]> {
- // Instruction operands.
- bits<5> Dd;
- bits<5> Dn;
- bits<5> Dm;
-
- let Inst{15-12} = Dd{3-0};
- let Inst{22} = Dd{4};
- let Inst{19-16} = Dn{3-0};
- let Inst{7} = Dn{4};
- let Inst{3-0} = Dm{3-0};
- let Inst{5} = Dm{4};
-
+ (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
+ OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
+ [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
let isCommutable = Commutable;
}
// Same as N3VD but no data type.
OpcodeStr, Dt, "$Qd, $Qn, $Qm", "",
[(set QPR:$Qd, (ResTy (OpNode (OpTy QPR:$Qn), (OpTy QPR:$Qm))))]> {
let isCommutable = Commutable;
-
- bits<4> Qd;
- bits<4> Qn;
- bits<4> Qm;
-
- let Inst{15-13} = Qd{2-0};
- let Inst{22} = Qd{3};
- let Inst{12} = 0;
- let Inst{19-17} = Qn{2-0};
- let Inst{7} = Qn{3};
- let Inst{16} = 0;
- let Inst{3-1} = Qm{2-0};
- let Inst{5} = Qm{3};
- let Inst{0} = 0;
}
class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
InstrItinClass itin, string OpcodeStr,
Format f, InstrItinClass itin, string OpcodeStr, string Dt,
ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
: N3V<op24, op23, op21_20, op11_8, 0, op4,
- (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), f, itin,
- OpcodeStr, Dt, "$Dd, $Dn, $Dm", "",
- [(set DPR:$Dd, (ResTy (IntOp (OpTy DPR:$Dn), (OpTy DPR:$Dm))))]> {
+ (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
+ OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
+ [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
let isCommutable = Commutable;
-
- // Instruction operands.
- bits<5> Dd;
- bits<5> Dn;
- bits<5> Dm;
-
- let Inst{15-12} = Dd{3-0};
- let Inst{22} = Dd{4};
- let Inst{19-16} = Dn{3-0};
- let Inst{7} = Dn{4};
- let Inst{3-0} = Dm{3-0};
- let Inst{5} = Dm{4};
}
class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
Format f, InstrItinClass itin, string OpcodeStr, string Dt,
ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
: N3V<op24, op23, op21_20, op11_8, 1, op4,
- (outs QPR:$Qd), (ins QPR:$Qn, QPR:$Qm), f, itin,
- OpcodeStr, Dt, "$Qd, $Qn, $Qm", "",
- [(set QPR:$Qd, (ResTy (IntOp (OpTy QPR:$Qn), (OpTy QPR:$Qm))))]> {
+ (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
+ OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
+ [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
let isCommutable = Commutable;
-
- // Instruction operands.
- bits<4> Qd;
- bits<4> Qn;
- bits<4> Qm;
-
- let Inst{15-13} = Qd{2-0};
- let Inst{22} = Qd{3};
- let Inst{12} = 0;
- let Inst{19-17} = Qn{2-0};
- let Inst{7} = Qn{3};
- let Inst{16} = 0;
- let Inst{3-1} = Qm{2-0};
- let Inst{5} = Qm{3};
- let Inst{0} = 0;
}
class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
string OpcodeStr, string Dt,
InstrItinClass itin, string OpcodeStr, string Dt,
ValueType Ty, SDNode MulOp, SDNode OpNode>
: N3V<op24, op23, op21_20, op11_8, 0, op4,
- (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
- OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
- [(set DPR:$dst, (Ty (OpNode DPR:$src1,
- (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
+ (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
+ OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
+ [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
+ (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
+
class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
string OpcodeStr, string Dt,
ValueType Ty, SDNode MulOp, SDNode ShOp>
string OpcodeStr, string Dt,
ValueType Ty, SDNode MulOp, SDNode ShOp>
: N3V<0, 1, op21_20, op11_8, 1, 0,
- (outs DPR:$dst),
- (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane),
+ (outs DPR:$Vd),
+ (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
NVMulSLFrm, itin,
- OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst",
- [(set (Ty DPR:$dst),
+ OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
+ [(set (Ty DPR:$Vd),
(Ty (ShOp (Ty DPR:$src1),
- (Ty (MulOp DPR:$src2,
- (Ty (NEONvduplane (Ty DPR_8:$src3),
+ (Ty (MulOp DPR:$Vn,
+ (Ty (NEONvduplane (Ty DPR_8:$Vm),
imm:$lane)))))))]>;
class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
SDNode MulOp, SDNode OpNode>
: N3V<op24, op23, op21_20, op11_8, 1, op4,
- (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, itin,
- OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
- [(set QPR:$dst, (Ty (OpNode QPR:$src1,
- (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
+ (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
+ OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
+ [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
+ (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
SDNode MulOp, SDNode ShOp>
InstrItinClass itin, string OpcodeStr, string Dt,
ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
: N3V<op24, op23, op21_20, op11_8, 0, op4,
- (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
- OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
- [(set QPR:$dst, (OpNode (TyQ QPR:$src1),
- (TyQ (MulOp (TyD DPR:$src2),
- (TyD DPR:$src3)))))]>;
+ (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
+ OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
+ [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
+ (TyQ (MulOp (TyD DPR:$Vn),
+ (TyD DPR:$Vm)))))]>;
class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
InstrItinClass itin, string OpcodeStr, string Dt,
ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
InstrItinClass itin, string OpcodeStr, string Dt,
ValueType TyQ, ValueType TyD, Intrinsic IntOp>
: N3V<op24, op23, op21_20, op11_8, 0, op4,
- (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
- OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
- [(set QPR:$dst,
- (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
+ (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
+ OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
+ [(set QPR:$Vd,
+ (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
string OpcodeStr, string Dt,
ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
[(set QPR:$Qd, (OpNode (TyQ (ExtOp (TyD DPR:$Dn))),
(TyQ (ExtOp (TyD DPR:$Dm)))))]> {
let isCommutable = Commutable;
-
- // Instruction operands.
- bits<4> Qd;
- bits<5> Dn;
- bits<5> Dm;
-
- let Inst{15-13} = Qd{2-0};
- let Inst{22} = Qd{3};
- let Inst{12} = 0;
- let Inst{19-16} = Dn{3-0};
- let Inst{7} = Dn{4};
- let Inst{3-0} = Dm{3-0};
- let Inst{5} = Dm{4};
-
- let isCommutable = Commutable;
}
// Long 3-register intrinsics with explicit extend (VABDL).
[(set QPR:$Qd, (OpNode (TyQ QPR:$Qn),
(TyQ (ExtOp (TyD DPR:$Dm)))))]> {
let isCommutable = Commutable;
-
- // Instruction operands.
- bits<4> Qd;
- bits<4> Qn;
- bits<5> Dm;
-
- let Inst{15-13} = Qd{2-0};
- let Inst{22} = Qd{3};
- let Inst{12} = 0;
- let Inst{19-17} = Qn{2-0};
- let Inst{7} = Qn{3};
- let Inst{16} = 0;
- let Inst{3-0} = Dm{3-0};
- let Inst{5} = Dm{4};
}
// Pairwise long 2-register intrinsics, both double- and quad-register.
def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
NEONvcge, 0>;
// For disassembly only.
+// FIXME: This instruction's encoding MAY NOT BE correct.
defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
"$dst, $src, #0">;
// For disassembly only.
+// FIXME: This instruction's encoding MAY NOT BE correct.
defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
"$dst, $src, #0">;