Add Mac OS X compatible JIT callback routine.

[oota-llvm.git] / lib / Target / ARM / ARMInstrThumb.td

diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index 7cfec81c868d91abc9f73e91d26c9ff4769e6bc4..72dae87a1e3b215fd73a158f564f6545fc810517 100644 (file)
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -2,8 +2,8 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by Chris Lattner and is distributed under the
-// University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
@@ -18,51 +18,6 @@
 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
                       [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
 
-// TI - Thumb instruction.
-
-// ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
-class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
-  list<Predicate> Predicates = [IsThumb];
-}
-
-class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
-  list<Predicate> Predicates = [IsThumb, HasV5T];
-}
-
-class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
-             string asm, string cstr, list<dag> pattern>
-  // FIXME: Set all opcodes to 0 for now.
-  : InstARM<0, am, sz, IndexModeNone, ThumbFrm, cstr> {
-  let OutOperandList = outs;
-  let InOperandList = ins;
-  let AsmString   = asm;
-  let Pattern = pattern;
-  list<Predicate> Predicates = [IsThumb];
-}
-
-class TI<dag outs, dag ins, string asm, list<dag> pattern>
-  : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>;
-class TI1<dag outs, dag ins, string asm, list<dag> pattern>
-  : ThumbI<outs, ins, AddrModeT1, Size2Bytes, asm, "", pattern>;
-class TI2<dag outs, dag ins, string asm, list<dag> pattern>
-  : ThumbI<outs, ins, AddrModeT2, Size2Bytes, asm, "", pattern>;
-class TI4<dag outs, dag ins, string asm, list<dag> pattern>
-  : ThumbI<outs, ins, AddrModeT4, Size2Bytes, asm, "", pattern>;
-class TIs<dag outs, dag ins, string asm, list<dag> pattern>
-  : ThumbI<outs, ins, AddrModeTs, Size2Bytes, asm, "", pattern>;
-
-// Two-address instructions
-class TIt<dag outs, dag ins, string asm, list<dag> pattern>
-  : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
-
-// BL, BLX(1) are translated by assembler into two instructions
-class TIx2<dag outs, dag ins, string asm, list<dag> pattern>
-  : ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>;
-
-// BR_JT instructions
-class TJTI<dag outs, dag ins, string asm, list<dag> pattern>
-  : ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>;
-
 def imm_neg_XFORM : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(-(int)N->getValue(), MVT::i32);
 }]>;
@@ -188,7 +143,7 @@ let isReturn = 1, isTerminator = 1 in {
 }
 
 // FIXME: remove when we have a way to marking a MI with these properties.
-let isLoad = 1, isReturn = 1, isTerminator = 1 in
+let isReturn = 1, isTerminator = 1 in
 def tPOP_RET : TI<(outs reglist:$dst1, variable_ops), (ins),
                    "pop $dst1", []>;
 
@@ -237,7 +192,7 @@ let isBranch = 1, isTerminator = 1 in
 //  Load Store Instructions.
 //
 
-let isLoad = 1 in {
+let isSimpleLoad = 1 in
 def tLDR : TI4<(outs GPR:$dst), (ins t_addrmode_s4:$addr),
                "ldr $dst, $addr",
                [(set GPR:$dst, (load t_addrmode_s4:$addr))]>;
@@ -258,27 +213,28 @@ def tLDRSH : TI2<(outs GPR:$dst), (ins t_addrmode_rr:$addr),
                  "ldrsh $dst, $addr",
                  [(set GPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
 
+let isSimpleLoad = 1 in
 def tLDRspi : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr),
                   "ldr $dst, $addr",
                   [(set GPR:$dst, (load t_addrmode_sp:$addr))]>;
 
 // Special instruction for restore. It cannot clobber condition register
 // when it's expanded by eliminateCallFramePseudoInstr().
+let isSimpleLoad = 1, mayLoad = 1 in
 def tRestore : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr),
                     "ldr $dst, $addr", []>;
 
 // Load tconstpool
+let isSimpleLoad = 1 in
 def tLDRpci : TIs<(outs GPR:$dst), (ins i32imm:$addr),
                   "ldr $dst, $addr",
                   [(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
 
 // Special LDR for loads from non-pc-relative constpools.
-let isReMaterializable = 1 in
+let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1 in
 def tLDRcp  : TIs<(outs GPR:$dst), (ins i32imm:$addr),
                   "ldr $dst, $addr", []>;
-} // isLoad
 
-let isStore = 1 in {
 def tSTR : TI4<(outs), (ins GPR:$src, t_addrmode_s4:$addr),
                "str $src, $addr",
                [(store GPR:$src, t_addrmode_s4:$addr)]>;
@@ -295,6 +251,7 @@ def tSTRspi : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr),
                    "str $src, $addr",
                    [(store GPR:$src, t_addrmode_sp:$addr)]>;
 
+let mayStore = 1 in {
 // Special instruction for spill. It cannot clobber condition register
 // when it's expanded by eliminateCallFramePseudoInstr().
 def tSpill : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr),
@@ -307,11 +264,11 @@ def tSpill : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr),
 
 // TODO: A7-44: LDMIA - load multiple
 
-let isLoad = 1 in
+let mayLoad = 1 in
 def tPOP : TI<(outs reglist:$dst1, variable_ops), (ins),
                "pop $dst1", []>;
 
-let isStore = 1 in
+let mayStore = 1 in
 def tPUSH : TI<(outs), (ins reglist:$src1, variable_ops),
                 "push $src1", []>;
 
@@ -586,10 +543,6 @@ def : ThumbPat<(extloadi1  t_addrmode_s1:$addr),  (tLDRB t_addrmode_s1:$addr)>;
 def : ThumbPat<(extloadi8  t_addrmode_s1:$addr),  (tLDRB t_addrmode_s1:$addr)>;
 def : ThumbPat<(extloadi16 t_addrmode_s2:$addr),  (tLDRH t_addrmode_s2:$addr)>;
 
-// truncstore i1 -> truncstore i8
-def : ThumbPat<(truncstorei1 GPR:$src, t_addrmode_s1:$dst), 
-               (tSTRB GPR:$src, t_addrmode_s1:$dst)>;
-
 // Large immediate handling.
 
 // Two piece imms.