Some random comment, naming, and format changes.

[oota-llvm.git] / lib / Target / ARM / ARMInstrThumb.td

diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index bad7740c72b6756d3ccb9b61ede2c41d825302e9..ae7a5c00bd74da3f3de34e9c65cd8a4ec863b926 100644 (file)
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -223,6 +223,7 @@ def t_addrmode_sp : Operand<i32>,
 def t_addrmode_pc : Operand<i32> {
   let EncoderMethod = "getAddrModePCOpValue";
   let DecoderMethod = "DecodeThumbAddrModePC";
+  let PrintMethod = "printThumbLdrLabelOperand";
 }
 
 //===----------------------------------------------------------------------===//
@@ -681,41 +682,6 @@ def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
   let Inst{7-0} = addr;
 }
 
-// Atomic loads. These pseudos expand to the loads above, but the have mayStore
-// = 1 so they can't be reordered.
-let mayLoad = 1, mayStore = 1, hasSideEffects = 0 in {
-let AM = AddrModeT1_1 in {
-def ATOMIC_tLDRBi : tPseudoExpand<(outs tGPR:$Rt),
-                                   (ins t_addrmode_is1:$addr, pred:$p),
-                                   2, IIC_iLoad_bh_i, [],
-                              (tLDRBi tGPR:$Rt, t_addrmode_is1:$addr, pred:$p)>;
-def ATOMIC_tLDRBr : tPseudoExpand<(outs tGPR:$Rt),
-                                   (ins t_addrmode_rrs1:$addr, pred:$p),
-                                   2, IIC_iLoad_bh_r, [],
-                             (tLDRBr tGPR:$Rt, t_addrmode_rrs1:$addr, pred:$p)>;
-}
-let AM = AddrModeT1_2 in {
-def ATOMIC_tLDRHi : tPseudoExpand<(outs tGPR:$Rt),
-                                   (ins t_addrmode_is2:$addr, pred:$p),
-                                   2, IIC_iLoad_bh_i, [],
-                              (tLDRHi tGPR:$Rt, t_addrmode_is2:$addr, pred:$p)>;
-def ATOMIC_tLDRHr : tPseudoExpand<(outs tGPR:$Rt),
-                                   (ins t_addrmode_rrs2:$addr, pred:$p),
-                                   2, IIC_iLoad_bh_r, [],
-                             (tLDRHr tGPR:$Rt, t_addrmode_rrs2:$addr, pred:$p)>;
-}
-let AM = AddrModeT1_4 in {
-def ATOMIC_tLDRi  : tPseudoExpand<(outs tGPR:$Rt),
-                                   (ins t_addrmode_is4:$addr, pred:$p),
-                                   2, IIC_iLoad_i, [],
-                               (tLDRi tGPR:$Rt, t_addrmode_is4:$addr, pred:$p)>;
-def ATOMIC_tLDRr  : tPseudoExpand<(outs tGPR:$Rt),
-                                   (ins t_addrmode_rrs4:$addr, pred:$p),
-                                   2, IIC_iLoad_r, [],
-                              (tLDRr tGPR:$Rt, t_addrmode_rrs4:$addr, pred:$p)>;
-}
-}
-
 //===----------------------------------------------------------------------===//
 //  Load / store multiple Instructions.
 //
@@ -1281,10 +1247,6 @@ def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
                               [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
                              Requires<[IsThumb, IsIOS]>;
 
-let Defs = [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7, R12, CPSR ],
-    isBarrier = 1 in
-def tInt_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
-
 //===----------------------------------------------------------------------===//
 // Non-Instruction Patterns
 //
@@ -1369,17 +1331,17 @@ def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
             (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
 
 def : T1Pat<(atomic_load_8 t_addrmode_is1:$src),
-             (ATOMIC_tLDRBi t_addrmode_is1:$src)>;
+             (tLDRBi t_addrmode_is1:$src)>;
 def : T1Pat<(atomic_load_8 t_addrmode_rrs1:$src),
-             (ATOMIC_tLDRBr t_addrmode_rrs1:$src)>;
+             (tLDRBr t_addrmode_rrs1:$src)>;
 def : T1Pat<(atomic_load_16 t_addrmode_is2:$src),
-             (ATOMIC_tLDRHi t_addrmode_is2:$src)>;
+             (tLDRHi t_addrmode_is2:$src)>;
 def : T1Pat<(atomic_load_16 t_addrmode_rrs2:$src),
-             (ATOMIC_tLDRHr t_addrmode_rrs2:$src)>;
+             (tLDRHr t_addrmode_rrs2:$src)>;
 def : T1Pat<(atomic_load_32 t_addrmode_is4:$src),
-             (ATOMIC_tLDRi t_addrmode_is4:$src)>;
+             (tLDRi t_addrmode_is4:$src)>;
 def : T1Pat<(atomic_load_32 t_addrmode_rrs4:$src),
-             (ATOMIC_tLDRr t_addrmode_rrs4:$src)>;
+             (tLDRr t_addrmode_rrs4:$src)>;
 def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val),
              (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>;
 def : T1Pat<(atomic_store_8 t_addrmode_rrs1:$ptr, tGPR:$val),