// Define Thumb specific addressing modes.
+def t_brtarget : Operand<OtherVT> {
+ let EncoderMethod = "getThumbBRTargetOpValue";
+}
+
+def t_bcctarget : Operand<i32> {
+ let EncoderMethod = "getThumbBCCTargetOpValue";
+}
+
+def t_cbtarget : Operand<i32> {
+ let EncoderMethod = "getThumbCBTargetOpValue";
+}
+
+def t_bltarget : Operand<i32> {
+ let EncoderMethod = "getThumbBLTargetOpValue";
+}
+
+def t_blxtarget : Operand<i32> {
+ let EncoderMethod = "getThumbBLXTargetOpValue";
+}
+
def MemModeThumbAsmOperand : AsmOperandClass {
let Name = "MemModeThumb";
let SuperClasses = [];
//
def t_addrmode_s4 : Operand<i32>,
ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
- string EncoderMethod = "getAddrModeS4OpValue";
+ let EncoderMethod = "getAddrModeSOpValue";
let PrintMethod = "printThumbAddrModeS4Operand";
let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
let ParserMatchClass = MemModeThumbAsmOperand;
//
def t_addrmode_s2 : Operand<i32>,
ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
- string EncoderMethod = "getAddrModeS2OpValue";
+ let EncoderMethod = "getAddrModeSOpValue";
let PrintMethod = "printThumbAddrModeS2Operand";
let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
let ParserMatchClass = MemModeThumbAsmOperand;
//
def t_addrmode_s1 : Operand<i32>,
ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
- string EncoderMethod = "getAddrModeS1OpValue";
+ let EncoderMethod = "getAddrModeSOpValue";
let PrintMethod = "printThumbAddrModeS1Operand";
let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
let ParserMatchClass = MemModeThumbAsmOperand;
//
def t_addrmode_sp : Operand<i32>,
ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
+ let EncoderMethod = "getAddrModeThumbSPOpValue";
let PrintMethod = "printThumbAddrModeSPOperand";
let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
let ParserMatchClass = MemModeThumbAsmOperand;
}
+// t_addrmode_pc := <label> => pc + imm8 * 4
+//
+def t_addrmode_pc : Operand<i32> {
+ let EncoderMethod = "getAddrModePCOpValue";
+ let ParserMatchClass = MemModeThumbAsmOperand;
+}
+
//===----------------------------------------------------------------------===//
// Miscellaneous Instructions.
//
Uses = [SP] in {
// Also used for Thumb2
def tBL : TIx2<0b11110, 0b11, 1,
- (outs), (ins bltarget:$func, variable_ops), IIC_Br,
+ (outs), (ins t_bltarget:$func, variable_ops), IIC_Br,
"bl\t$func",
[(ARMtcall tglobaladdr:$func)]>,
Requires<[IsThumb, IsNotDarwin]> {
- bits<24> func;
- let Inst{26} = func{23};
+ bits<21> func;
let Inst{25-16} = func{20-11};
- let Inst{13} = func{22};
- let Inst{11} = func{21};
- let Inst{10-0} = func{10-0};
+ let Inst{13} = 1;
+ let Inst{11} = 1;
+ let Inst{10-0} = func{10-0};
}
// ARMv5T and above, also used for Thumb2
def tBLXi : TIx2<0b11110, 0b11, 0,
- (outs), (ins i32imm:$func, variable_ops), IIC_Br,
+ (outs), (ins t_blxtarget:$func, variable_ops), IIC_Br,
"blx\t$func",
[(ARMcall tglobaladdr:$func)]>,
- Requires<[IsThumb, HasV5T, IsNotDarwin]>;
+ Requires<[IsThumb, HasV5T, IsNotDarwin]> {
+ bits<21> func;
+ let Inst{25-16} = func{20-11};
+ let Inst{13} = 1;
+ let Inst{11} = 1;
+ let Inst{10-1} = func{10-1};
+ let Inst{0} = 0; // func{0} is assumed zero
+ }
// Also used for Thumb2
def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24;
// ARMv4T
+ // FIXME: Should be a pseudo.
let isCodeGenOnly = 1 in
def tBX : TIx2<{?,?,?,?,?}, {?,?}, ?,
(outs), (ins tGPR:$func, variable_ops), IIC_Br,
Uses = [R7, SP] in {
// Also used for Thumb2
def tBLr9 : TIx2<0b11110, 0b11, 1,
- (outs), (ins pred:$p, bltarget:$func, variable_ops), IIC_Br,
- "bl${p}\t$func",
+ (outs), (ins pred:$p, t_bltarget:$func, variable_ops),
+ IIC_Br, "bl${p}\t$func",
[(ARMtcall tglobaladdr:$func)]>,
Requires<[IsThumb, IsDarwin]> {
- bits<24> func;
- let Inst{26} = func{23};
+ bits<21> func;
let Inst{25-16} = func{20-11};
- let Inst{13} = func{22};
- let Inst{11} = func{21};
- let Inst{10-0} = func{10-0};
+ let Inst{13} = 1;
+ let Inst{11} = 1;
+ let Inst{10-0} = func{10-0};
}
// ARMv5T and above, also used for Thumb2
def tBLXi_r9 : TIx2<0b11110, 0b11, 0,
- (outs), (ins pred:$p, i32imm:$func, variable_ops), IIC_Br,
- "blx${p}\t$func",
+ (outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
+ IIC_Br, "blx${p}\t$func",
[(ARMcall tglobaladdr:$func)]>,
- Requires<[IsThumb, HasV5T, IsDarwin]>;
+ Requires<[IsThumb, HasV5T, IsDarwin]> {
+ bits<21> func;
+ let Inst{25-16} = func{20-11};
+ let Inst{13} = 1;
+ let Inst{11} = 1;
+ let Inst{10-1} = func{10-1};
+ let Inst{0} = 0; // func{0} is assumed zero
+ }
// Also used for Thumb2
def tBLXr_r9 : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
// ARMv4T
let isCodeGenOnly = 1 in
+ // FIXME: Should be a pseudo.
def tBXr9 : TIx2<{?,?,?,?,?}, {?,?}, ?,
(outs), (ins tGPR:$func, variable_ops), IIC_Br,
"mov\tlr, pc\n\tbx\t$func",
let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
let isPredicable = 1 in
- def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
+ def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
"b\t$target", [(br bb:$target)]>,
- T1Encoding<{1,1,1,0,0,?}>;
+ T1Encoding<{1,1,1,0,0,?}> {
+ bits<11> target;
+ let Inst{10-0} = target;
+ }
// Far jump
+ // FIXME: Encoding. This should probably be a pseudo for tBL
let Defs = [LR] in
def tBfar : TIx2<0b11110, 0b11, 1, (outs), (ins brtarget:$target), IIC_Br,
"bl\t$target",[]>;
// FIXME: should be able to write a pattern for ARMBrcond, but can't use
// a two-value operand where a dag node expects two operands. :(
let isBranch = 1, isTerminator = 1 in
- def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br,
- "b$cc\t$target",
+ def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
+ "b${p}\t$target",
[/*(ARMbrcond bb:$target, imm:$cc)*/]>,
- T1Encoding<{1,1,0,1,?,?}>;
+ T1Encoding<{1,1,0,1,?,?}> {
+ bits<4> p;
+ bits<8> target;
+ let Inst{11-8} = p;
+ let Inst{7-0} = target;
+}
// Compare and branch on zero / non-zero
let isBranch = 1, isTerminator = 1 in {
- def tCBZ : T1I<(outs), (ins tGPR:$Rn, brtarget:$target), IIC_Br,
+ def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
"cbz\t$Rn, $target", []>,
T1Misc<{0,0,?,1,?,?,?}> {
// A8.6.27
let Inst{2-0} = Rn;
}
- def tCBNZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
+ def tCBNZ : T1I<(outs), (ins tGPR:$cmp, t_cbtarget:$target), IIC_Br,
"cbnz\t$cmp, $target", []>,
T1Misc<{1,0,?,1,?,?,?}> {
// A8.6.27
"ldr", "\t$Rt, $addr",
[(set tGPR:$Rt, (load t_addrmode_s4:$addr))]>;
-def tLDRi: // A8.6.57
+def tLDRi : // A8.6.57
T1pILdStEncodeImm<0b0110, 1, (outs tGPR:$Rt), (ins t_addrmode_s4:$addr),
AddrModeT1_4, IIC_iLoad_r,
"ldr", "\t$Rt, $addr",
[(set tGPR:$Rt, (zextloadi8 t_addrmode_s1:$addr))]>;
def tLDRBi : // A8.6.61
- T1pILdStEncodeImm<0b0111, 1, (outs tGPR:$dst), (ins t_addrmode_s1:$addr),
+ T1pILdStEncodeImm<0b0111, 1, (outs tGPR:$Rt), (ins t_addrmode_s1:$addr),
AddrModeT1_1, IIC_iLoad_bh_r,
- "ldrb", "\t$dst, $addr",
+ "ldrb", "\t$Rt, $addr",
[]>;
def tLDRH : // A8.6.76
"ldrh", "\t$dst, $addr",
[(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
-def tLDRHi: // A8.6.73
- T1pILdStEncodeImm<0b1000, 1, (outs tGPR:$dst), (ins t_addrmode_s2:$addr),
+def tLDRHi : // A8.6.73
+ T1pILdStEncodeImm<0b1000, 1, (outs tGPR:$Rt), (ins t_addrmode_s2:$addr),
AddrModeT1_2, IIC_iLoad_bh_r,
- "ldrh", "\t$dst, $addr",
+ "ldrh", "\t$Rt, $addr",
[]>;
let AddedComplexity = 10 in
[(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
let canFoldAsLoad = 1 in
-def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
- "ldr", "\t$dst, $addr",
- [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>,
- T1LdStSP<{1,?,?}>;
+def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
+ "ldr", "\t$Rt, $addr",
+ [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
+ T1LdStSP<{1,?,?}> {
+ bits<3> Rt;
+ bits<8> addr;
+ let Inst{10-8} = Rt;
+ let Inst{7-0} = addr;
+}
// Special instruction for restore. It cannot clobber condition register
// when it's expanded by eliminateCallFramePseudoInstr().
let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1 in
+// FIXME: Pseudo for tLDRspi
def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
"ldr", "\t$dst, $addr", []>,
T1LdStSP<{1,?,?}>;
// Load tconstpool
// FIXME: Use ldr.n to work around a Darwin assembler bug.
let canFoldAsLoad = 1, isReMaterializable = 1 in
-def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins i32imm:$addr), IIC_iLoad_i,
+def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
"ldr", ".n\t$Rt, $addr",
[(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
T1Encoding<{0,1,0,0,1,?}> {
// A6.2 & A8.6.59
bits<3> Rt;
+ bits<8> addr;
let Inst{10-8} = Rt;
- // FIXME: Finish for the addr.
+ let Inst{7-0} = addr;
}
// Special LDR for loads from non-pc-relative constpools.
let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
isReMaterializable = 1 in
-def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoad_i,
- "ldr", "\t$dst, $addr", []>,
- T1LdStSP<{1,?,?}>;
+def tLDRcp : T1pIs<(outs tGPR:$Rt), (ins i32imm:$addr), IIC_iLoad_i,
+ "ldr", "\t$Rt, $addr", []>,
+ T1LdStSP<{1,?,?}> {
+ // A6.2 & A8.6.57 T2
+ bits<3> Rt;
+ bits<8> addr;
+ let Inst{10-8} = Rt;
+ let Inst{7-0} = addr;
+}
def tSTR : // A8.6.194
T1pILdStEncode<0b000, (outs), (ins tGPR:$src, t_addrmode_s4:$addr),
[(store tGPR:$src, t_addrmode_s4:$addr)]>;
def tSTRi : // A8.6.192
- T1pILdStEncodeImm<0b0110, 0, (outs), (ins tGPR:$src, t_addrmode_s4:$addr),
+ T1pILdStEncodeImm<0b0110, 0, (outs), (ins tGPR:$Rt, t_addrmode_s4:$addr),
AddrModeT1_4, IIC_iStore_r,
- "str", "\t$src, $addr",
+ "str", "\t$Rt, $addr",
[]>;
def tSTRB : // A8.6.197
[(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
def tSTRBi : // A8.6.195
- T1pILdStEncodeImm<0b0111, 0, (outs), (ins tGPR:$src, t_addrmode_s1:$addr),
+ T1pILdStEncodeImm<0b0111, 0, (outs), (ins tGPR:$Rt, t_addrmode_s1:$addr),
AddrModeT1_1, IIC_iStore_bh_r,
- "strb", "\t$src, $addr",
+ "strb", "\t$Rt, $addr",
[]>;
def tSTRH : // A8.6.207
[(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
def tSTRHi : // A8.6.205
- T1pILdStEncodeImm<0b1000, 0, (outs), (ins tGPR:$src, t_addrmode_s2:$addr),
+ T1pILdStEncodeImm<0b1000, 0, (outs), (ins tGPR:$Rt, t_addrmode_s2:$addr),
AddrModeT1_2, IIC_iStore_bh_r,
- "strh", "\t$src, $addr",
+ "strh", "\t$Rt, $addr",
[]>;
-def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
- "str", "\t$src, $addr",
- [(store tGPR:$src, t_addrmode_sp:$addr)]>,
- T1LdStSP<{0,?,?}>;
+def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
+ "str", "\t$Rt, $addr",
+ [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
+ T1LdStSP<{0,?,?}> {
+ bits<3> Rt;
+ bits<8> addr;
+ let Inst{10-8} = Rt;
+ let Inst{7-0} = addr;
+}
let mayStore = 1, neverHasSideEffects = 1 in
// Special instruction for spill. It cannot clobber condition register when it's
// expanded by eliminateCallFramePseudoInstr().
+// FIXME: Pseudo for tSTRspi
def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
"str", "\t$src, $addr", []>,
T1LdStSP<{0,?,?}>;
let Inst{7-0} = imm8;
}
-def tCMPzi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi,
- "cmp", "\t$Rn, $imm8",
- [(ARMcmpZ tGPR:$Rn, imm0_255:$imm8)]>,
- T1General<{1,0,1,?,?}> {
- // A8.6.35
- bits<3> Rn;
- let Inst{10-8} = Rn;
- let Inst{7-0} = 0x00;
-}
-
// CMP register
def tCMPr : // A8.6.36 T1
T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
"cmp", "\t$Rn, $Rm",
[(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
-def tCMPzr : // A8.6.36 T1
- T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iCMPr,
- "cmp", "\t$Rn, $Rm",
- [(ARMcmpZ tGPR:$Rn, tGPR:$Rm)]>;
-
def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
"cmp", "\t$Rn, $Rm", []>,
T1Special<{0,1,?,?}> {
let Inst{6-3} = Rm;
let Inst{2-0} = Rn{2-0};
}
-def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
- "cmp", "\t$lhs, $rhs", []>,
- T1Special<{0,1,?,?}> {
- // A8.6.36 T2
- bits<4> Rm;
- bits<4> Rn;
- let Inst{7} = Rn{3};
- let Inst{6-3} = Rm;
- let Inst{2-0} = Rn{2-0};
-}
-
} // isCompare = 1, Defs = [CPSR]
// Non-Instruction Patterns
//
+// Comparisons
+def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
+ (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
+def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
+ (tCMPr tGPR:$Rn, tGPR:$Rm)>;
+
// Add with carry
def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
(tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
projects / oota-llvm.git / blobdiff